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Newbie
Newbie
9,550 Views
Registered: ‎04-12-2016

Reference Design for Xilinx JESD204B and TI ADS42JB69 Interoperability Report

Hello Xilinx Experts,

 

We have a Zynq 7100 and a TI ADS42JB69 that we are trying to interface. We have compiled the JESD IP core, and are able to communicate with the ADC via SPI; however, we seem to be having some problems with ensuring that all the JESD parameters are coordinated.

 

Because this part is used in a joint Xilinx/TI interoperability report, we are are looking for the reference design that is described in it (the JESD204B Xilinx/Ti ADS42JB69 Interoperability Report from 2014 -- http://www.ti.com/lit/ml/slal212/slal212.pdf). We would like to know what settings were used for the IP core, the reference clock (TI LMK04828) at 62.5 MHz, and how the two boards were interconnected (we are assuming the FMC connector).

 

Any VHDL code would also be appreciated. We have access to the JESD204B TI Reference design that was significantly more recent (2015), but that seems to be far more complicated and does not specify the reference clock parameters for the Ti ADS42JB69 Evaluation board.

 

Any assistance you can provide would be greatly appreciated.

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Moderator
Moderator
8,891 Views
Registered: ‎02-16-2010

the link you mentioned about Xilinx/Ti ADS42JB69 Interoperability Report from 2014 is not working now.

Since the report is from TI, could you check with them?
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Newbie
Newbie
8,861 Views
Registered: ‎04-12-2016

It seems like the link was being hyperlinked inappropriately (extra parenthesis at the end). Here it is, and it should work.

 

http://www.ti.com/lit/ml/slal212/slal212.pdf

 

We have been in contact with TI and with Mr. David Ramsey from Xilinx. It appears that there has been some loss of organizational knowledge. If you could please look into it on your side, we'll continue to try and work on getting information from TI.

 

Thanks for your help again.

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