cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
7,821 Views
Registered: ‎08-04-2014

Reg: SRIO protocol

Jump to solution

Hi,

 

Can anyone help me  how to send ethernet packetts through SRIO protocol  ?

 

 

Thanks

Sunitha

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
14,712 Views
Registered: ‎07-11-2011

@sunitha_vtpl, how to send user defined packets is a difefrenet topic, I am usure if example design has any provision to send them with simple change, i would suggest you to check documentation and crak teh RTL, if that does not help, please start a new thread.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos
5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
7,817 Views
Registered: ‎07-11-2011

@sunitha_vtpl, we do not have refernce designs to send ethernet packets over SRIO.

But SRIO supports Hello and Streaming formats. You can have an AXI Interconnect  that interfcaes with AXI interface of Ethernet and  AXI interface of SRIO and establish the connectivity. You may need some glue logic to have undersatnding of each other packet interfaces.

 

Hope this helps

 

-Vanitha.

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Highlighted
Adventurer
Adventurer
7,776 Views
Registered: ‎08-04-2014

Hi Vanitha,

 

Thanks for your reply,

SRIO interface between PowerPC and FPGA.

We are using srio_v5.6 IPcore in virtex 5 FPGA(XC5VFX200T)with example design.In Power PC  "RIO_Ethernet " type is used, so i want change my logic in FPGA.

 

As mentioned in UG503 pg No:245 "User Defined Packets" what i have understood is that we can use userdefined packets for ethernet communication in SRIO.Am i correct? or what is the option to communicate with PowerPC?

 

Thanks

Sunitha

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,771 Views
Registered: ‎07-11-2011

@sunitha_vtpl If the packet types give in UG do not suit your power PC/design requieremnts you can go for user defined packets, this should not have any issue any in TX direction.

 

-Vanitha

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Highlighted
Adventurer
Adventurer
7,764 Views
Registered: ‎08-04-2014

Hi,

 

Thanks for your reply,

Sorry it is not Power PC it is Processor,If i use "User defined Packets " what i need to change in example design so that i can use ethernet comunication?

I have changed FTYPE and TTYPE, but it did'nt show any effect,So are there any changes require in example design?

 

Thanks 

Sunitha

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
14,713 Views
Registered: ‎07-11-2011

@sunitha_vtpl, how to send user defined packets is a difefrenet topic, I am usure if example design has any provision to send them with simple change, i would suggest you to check documentation and crak teh RTL, if that does not help, please start a new thread.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos