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Adventurer
Adventurer
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Registered: ‎08-04-2014

Regarding SRIO

HI,

 

We are interfacing SRIO V5.6 with virtex5 device. when i am doing simulation with Example design i am not getting data on Ireq_data signal. I searched the path where i am strucking.I found that vio_control signal is not cumnig from virtual input output IP core, and moreover control0 signal in HIGH impedance state ,which comes from ICON IP core.

 

Here i am instantiating two IP cores.

 

SRIO_ICON srio_icon

(

.CONTROL0(control0),

.CONTROL1(control1),

.CONTROL2(control2)

)

 

 

SRIO_VIO srio_vio

(

 

.Control(control0),

.CLK(lnk_clk),

.SYNC_IN(vio_display),

.SYNC_OUT(vio_control)

)

 

Please give me reply as early as possible..

 

Thanks 

Sunitha

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