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sunitha_vtpl
Adventurer
Adventurer
9,194 Views
Registered: ‎08-04-2014

Regarding Serial Rapid IO

Hi,

 

We are using SRIO 5.6 version IP core with virtex5(XC5VFX200T).Can u please give details where we can observe writting and reading data in Example design.

 

Thanks

Sunitha

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yenigal
Xilinx Employee
Xilinx Employee
9,189 Views
Registered: ‎02-06-2013

 

Hi

 

Check the below doc

 

http://www.xilinx.com/Attachment/Xilinx_Answer_50166_SRIO_Debugging_Packet_Analysis_Guide_ver1.pdf

Regards,

Satish

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vsrunga
Xilinx Employee
Xilinx Employee
9,187 Views
Registered: ‎07-11-2011

Hi,

 

Please refer ds696 User (Logical Layer) Interfac section and its timing diagrams

http://www.xilinx.com/support/documentation/ip_documentation/srio_ds696.pdf

 

 

Regards,

Vanitha

 

 

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sunitha_vtpl
Adventurer
Adventurer
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Registered: ‎08-04-2014

Thank you,

 

Is it suitable for SRIO version 5.6 ? Because it is not comes under Gen2.

 

Thank

Sunitha

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sunitha_vtpl
Adventurer
Adventurer
9,141 Views
Registered: ‎08-04-2014

Hi,

We have seen Xilinx 50166 answer record.It is for Gen2.When i compared to SRIO version 5.6 some signals are missing.

There is no link_initialized signal in SRIO V5.6, so how can we know the link establishment ?.

We are getting HIGH on lnk_porterr_n .But in Answer record Figure 6 port_error is LOW. which one is correct?

We are not getting exact data on tx_data and rx_data as shown in answer record figure7. You can observe in attached file.
Please tell me whether it is correct or not?

Thanks
Sunitha

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