09-16-2014 10:19 PM
We are using SRIO 5.6 version IP core with virtex5(XC5VFX200T).Can u please give details where we can observe writting and reading data in Example design.
09-16-2014 10:23 PM
Check the below doc
09-16-2014 10:24 PM
Please refer ds696 User (Logical Layer) Interfac section and its timing diagrams
09-18-2014 02:48 AM
We have seen Xilinx 50166 answer record.It is for Gen2.When i compared to SRIO version 5.6 some signals are missing.
There is no link_initialized signal in SRIO V5.6, so how can we know the link establishment ?.
We are getting HIGH on lnk_porterr_n .But in Answer record Figure 6 port_error is LOW. which one is correct?
We are not getting exact data on tx_data and rx_data as shown in answer record figure7. You can observe in attached file.
Please tell me whether it is correct or not?