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Adventurer
Adventurer
7,574 Views
Registered: ‎08-04-2014

Regarding Serial Rapid IO

Hi,

 

We are using SRIO V5.6 with XC5VFX200T-11738 configuration.We have generated IPcore by using core generator.when we open exmple design,initially some files are taken as  .ngc files.

 

srio_icon.ngc

srio_vio.ngc

rio_ila.ngc

phy_ila.ngc

 

but when we run "xtclsh create_ise_prj.tcl build project" as per UG 503,.NGC files became a .XCO files. 

srio_icon.xco

srio_vio.xco

rio_ila.xco

phy_ila.xco

 

so my doubt is which one we should add in project .NGC or .XCO files?

 

Thanks 

Sunitha

 

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2 Replies
Xilinx Employee
Xilinx Employee
7,562 Views
Registered: ‎02-06-2013

Hi

 

Refer below links which will answer your queries

 

http://forums.xilinx.com/t5/Connectivity/SRIO-v2-2-My-first-IP-core/td-p/415993

 

http://forums.xilinx.com/t5/Connectivity/how-to-use-created-ip-core-serial-rapidIO-v5-5-in-my-design/td-p/105391

 

Regards,

Satish

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Adventurer
Adventurer
7,555 Views
Registered: ‎08-04-2014

Thanks for reply.

 

I have generated bitsream file.But when i am doing simulation i am not getting data on i_req_data.

 

first of all i am not getting data on vio_control and control0 signal is in HIGH Impedance state.

 

SRIO_VIO srio_vio

(

 

.Control(control0),

.CLK(lnk_clk),

.SYNC_IN(vio_display),

.SYNC_OUT(vio_control)

)

 

Thanks

sunitha

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