10-07-2019 09:02 AM
Hello All,
I have been trying to develop a core for Nexys 4 board, which uses RMII PHY interface. Since the design I am planning to use has an GMII interface, I tried using an RTL module to convert design interface from GMII to MII and then, the MII to RMII core in the IP catalog (shown below). However, I noticed that the MII to RMII core is a discontinued core. May I know if there is an alternative core?
Thank you!
NJ
10-08-2019 03:47 AM
Hi @najath_akram ,
Unfortunately, we do not have a replacement core for MII2RMII.
10-08-2019 03:47 AM
Hi @najath_akram ,
Unfortunately, we do not have a replacement core for MII2RMII.
10-08-2019 07:25 AM
Thank you very much.
Is there any alternative way, or any example projects that I could go through to see, how to map MII or GMII interface to SGMII, RGMII and RMII ?
NJ
10-08-2019 08:38 AM
Hi @najath_akram ,
We have GMII2RGMII shim core for a GMII to RGMII interface. We also have PCS/PMA or SGMII core on PL for a GMII to SGMII/1000BASEX interface. For the latter, we have provided XAPP1305/1306 (for ZU+ devices) and XAPP1026/XAPP1082 (for Zynq) as reference design examples.
10-08-2019 12:54 PM
Hi @najath_akram ,
As a side note, the MII to RMII core is provided with all source files so you could potentially copy it in a custom directory and continue to use it with a newer version of Vivado.
10-09-2019 01:56 PM
Thank you very much. I will look into that!
12-23-2019 11:41 AM
06-02-2020 06:29 AM
Where could find the sources file ?
06-02-2020 06:48 AM
If you have installed Vivado in any version previous than 2019.1, you can find this IP source files at:
Xilinx/Vivado/2019.1/data/ip/xilinx/mii_to_rmii_v2_0
06-03-2020 06:46 AM