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378 Views
Registered: ‎07-08-2019

SGMII interface mdc clock is not generated in ARTIX 7 using AXI 1G/2.5G ethernet subsystem IP

Hi,

 

I am using AXI Ethernet subsystem ip and configured it in SGMII mode for connected to MARVEL IC 88E1111-B2-BAB1I000. The PHY address has been set to 0 is IP. I have used the SDK Ethernet example design available for the testing.

I have checked the GTH clock which is 125MHz and is fine and PLL lock has happened. But I am not able to see the MDC clock being generated. Also I have probed the user clocks through ILA and it looks fine. I am not able debug further.

can you tell me the possible reasons for MDC clock for not getting generated ?

Also suggest further ways for debugging the MDC clock.

 

 

Thanks and Regards

Raghu S

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fincs
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Adventurer
357 Views
Registered: ‎03-21-2016

In my opinion, the clock on the bus MDIO appears only when accessing the registers that are located on the bus. Moreover, the clock signal frequency is low, usually no more than 2.5 MHz.
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Registered: ‎07-08-2019

Hi,

Since I have used SDK Ethernet example design, I have put mdc clock in trigger in ILA and then run the application. But I didn't get any clock on mdc pin.

 

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