cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
284 Views
Registered: ‎12-26-2017

SGMII link down sometimes , but restart or reset the whole design , it works ok

HI,

i am using the SGMII ip and a hardware PHY (88E1111, marvell) to create a ethernet solution, the vivado is vivado 2019.1, and the FPGA is V7,690T. it works ok when i use the JTAG to debug, but when i download the .bin file to the flash, and disconnect the JTAG, sometimes it cannot work , and the status_vector[0], that is the link of the SGMII, is low, at this time , if i restart the device , or i put the reset button to reset the whole device, it works ok ,the link of the SGMII, goes to high. so what is the problem ? i donot know what is the key point.  

Thank you very much!

0 Kudos
7 Replies
Highlighted
Scholar
Scholar
257 Views
Registered: ‎08-07-2014

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

@zhipengzhao,

I think you should first determine if the bitfile transfer to flash and from flash to FPGA is occuring properly by implementing CRC checks. Have you done that?

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
248 Views
Registered: ‎12-26-2017

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

HI dpaul24,

thank you. the binfile is generated as the bitfile at the same time, and i think from flash to FPGA is occuring properly because the LED on the board is lighting properly, the LED is testing the FPGA whether works on or not.

0 Kudos
Highlighted
Visitor
Visitor
95 Views
Registered: ‎12-26-2017

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

is there some suggestions for me? hope to get suggestions from you, thanks!

0 Kudos
Highlighted
Moderator
Moderator
86 Views
Registered: ‎12-04-2016

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

Hi @zhipengzhao 

Also, please check on the si570 clock frequency being set properly in non-working case?

What changes have you made to device tree? Please share the kernel boot log for non-working case

 

Best Regards

Shabbir

0 Kudos
Highlighted
Visitor
Visitor
75 Views
Registered: ‎12-26-2017

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

HI, Moderator, thank you!

what does that mean? si570 clock frequency? is that the reference clock ? 

What changes have you made to device tree? Please share the kernel boot log for non-working case. i can not get your point ,there is only a FPGA V7 690T in my design. anyway ,thank you very much.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
41 Views
Registered: ‎05-01-2013

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

1. Does the link down happen only at the startup or after some time?

2. What's the link partner? Does it happen in GT PMA near end loopback mode?

3. If SGMII startup earlier than the link partner, I'll suggest you do one more GT RXRESET after the link partner is up.

0 Kudos
Highlighted
Visitor
Visitor
31 Views
Registered: ‎12-26-2017

Re: SGMII link down sometimes , but restart or reset the whole design , it works ok

HI, 

1. Does the link down happen only at the startup or after some time?

only at the startup.

2. What's the link partner? Does it happen in GT PMA near end loopback mode?

the link partner is the ethernet PHY(88E1111, marvell).

3. If SGMII startup earlier than the link partner, I'll suggest you do one more GT RXRESET after the link partner is up.

i do one more GT RXRESET ,and i reset the PHY also , but it does not work . i think i would attempt to do one more GT RXRESET only, and then see what happened.

0 Kudos