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Observer
Observer
5,910 Views
Registered: ‎10-28-2013

SRIO connect to AXI-Lite interface

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Hi! Tools - Vivado 2013.3. SRIO Gen.2 (v.3.0). How to connect SRIO core to the Microblaze processor. AXI-Lite interface is available (SRIO core) but there is no clock signal (s_axi_aclk) ?

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Xilinx Employee
Xilinx Employee
9,227 Views
Registered: ‎02-06-2013

Re: SRIO connect to AXI-Lite interface

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Hi

 

The log_clk_out will be used for the Axi lite interconnect Master interface axi clock.

 

 

 

Have a look at the attached snapshot showing the connections from the Microblaze to an interconnect and to the axi lite interface of the SRIO core and the clock connections.

 

Regards,

Satish

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SRIO_Microblaze.png
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Xilinx Employee
Xilinx Employee
9,228 Views
Registered: ‎02-06-2013

Re: SRIO connect to AXI-Lite interface

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Hi

 

The log_clk_out will be used for the Axi lite interconnect Master interface axi clock.

 

 

 

Have a look at the attached snapshot showing the connections from the Microblaze to an interconnect and to the axi lite interface of the SRIO core and the clock connections.

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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--------------------------------------------------​-------------------------------------------

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SRIO_Microblaze.png
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Observer
Observer
5,878 Views
Registered: ‎10-28-2013

Re: SRIO connect to AXI-Lite interface

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Hi! Thanks for the quick reply. Another issue - how to connect s_axi_maintr_rst?  (// Reset for maintr interface, on LOG clk domain). Thanks in advance.

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