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sunitha_vtpl
Adventurer
Adventurer
8,023 Views
Registered: ‎08-04-2014

SRIO interfacing

Hi,

 

we are using srioV5.6 IP core  with XC5VSX50T(ML506).As mentioned in userguide UG503, i understoode the path for Nwrite and Nread..

 

we are connecting loopback. when i observe the chipscope results, data on phy_tlnk_d and phy_rlnk_d are same but TX_DATA and RX_DATA  (these are input and outputs of rio_buffer)  are not same. you can observe the chipscope results in attached file.

 

so please tell me which signal i have to change to get  TX_DATA ,on RX_DATA  signal?

 

 

Regards

sunitha

 

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sunitha_vtpl
Adventurer
Adventurer
8,021 Views
Registered: ‎08-04-2014

Hi,

 

we are using srioV5.6 IP core  with XC5VSX50T(ML506).As mentioned in userguide UG503, i understoode the path for Nwrite and Nread..

 

we are connecting loopback. when i observe the chipscope results, data on phy_tlnk_d and phy_rlnk_d are same but TX_DATA and RX_DATA  (these are input and outputs of rio_buffer)  are not same. you can observe the chipscope results in attached file.

 

so please tell me which signal i have to change to get  TX_DATA ,on RX_DATA  signal?

 

 

Regards

sunitha

0 Kudos