08-30-2016 03:35 AM
I am connecting a virtex-7 FPGA to powerpc with SRIO at 2.5Gx4.
After downloading the bit file, only port_initialized went active, and the link_initialized didn't.
Is this a SI issue?
08-30-2016 03:39 AM - edited 08-30-2016 03:41 AM
what is your vivado and SRIO version . Are you able to run simulation correctly
Follow below steps.
1.You can do an ibert testing of the end to end link with SRIO protocol to determine the optimum transceiver settings which suits your hardware..
2. Enable Additional transceiver control and status ports option during core generation.
3. Use the top level ports generated by the core with the above option enabled to overwrite the default values with the optimum values from step 1.
I am assuming you are using full version license . When the hardware evaluation license time outs the entire logic of the core will be in reset state and you couldn't even see the requests being transmitted,so this is not the issue.
08-30-2016 04:11 AM
Check if giving additional resets brings the link up.
Try PMA loopback which will confirm all other things are fine and isolate SI on board as this does loopback on the transceiver.
I would expect notintable or disparity errors if there is SI but it looks there are not errors from the VIO snapshot.
08-30-2016 06:32 PM
I have tried to reset the link, it didn't work.
Since there is no notintable or disperr, I believe this is not about SI.
Is it possible that the link partner did not send any other control symbols except thos for the port_initialized to go up?
08-31-2016 12:33 AM - edited 08-31-2016 12:35 AM
I have checked the gtx tx data and rx data, as follow
You can see the FPGA kept receiving 1cbcfdbc80bcfdbcffbcfdbc0fbcfdbc, and repeatedly sending 05bcbcbc87bcbcbc80bcbcbc1cbcbcbc. There was no disperr or notintable.
It looks like the initialization process stuck at some phase.
09-16-2016 05:32 AM
Does the link partner has loopback options and is it able to link up with itself.
You can use the far end loopback options in the core to make sure the data is fine on the TX and RX if Link partner is able to link up with loopback options including the end to end path.