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Explorer
Explorer
4,965 Views
Registered: ‎06-22-2011

SRIO link problem

hi all,

 

I am connecting a virtex-7 FPGA to powerpc with SRIO at 2.5Gx4.

After downloading the bit file, only port_initialized went active, and the link_initialized didn't.

link_error.png

Is this a SI issue?

 

best regards

 

Xiang Chao

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5 Replies
Xilinx Employee
Xilinx Employee
4,961 Views
Registered: ‎08-01-2008

Re: SRIO link problem

what is your vivado and SRIO version . Are you able to run simulation correctly 
Follow below steps.

1.You can do an ibert testing of the end to end link with SRIO protocol to determine the optimum transceiver settings which suits your hardware..

2. Enable Additional transceiver control and status ports option during core generation.

3. Use the top level ports generated by the core with the above option enabled to overwrite the default values with the optimum values from step 1.

 

I am assuming you are using full version license .  When the hardware evaluation license time outs the entire logic of the core will be in reset state and you couldn't even see the requests being transmitted,so this is not the issue.

 

 

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
4,955 Views
Registered: ‎02-06-2013

Re: SRIO link problem

Hi

 

Check if giving additional resets brings the link up.

 

Try PMA loopback which will confirm all other things are fine and isolate SI on board as this does loopback on the transceiver.

 

I would expect notintable or disparity errors if there is SI but it looks there are not errors from the VIO snapshot.

Regards,

Satish

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Explorer
Explorer
4,937 Views
Registered: ‎06-22-2011

Re: SRIO link problem

hi,

 

I have tried to reset the link, it didn't work.

 

Since there is no notintable or disperr, I believe this is not about SI.

Is it possible that the link partner did not send any other control symbols except thos for the port_initialized to go up?

 

regards

 

Xiang Chao

 

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Explorer
Explorer
4,929 Views
Registered: ‎06-22-2011

Re: SRIO link problem

hi yenigal,

 

I have checked the gtx tx data and rx data, as follow

gtx.png

You can see the FPGA kept receiving 1cbcfdbc80bcfdbcffbcfdbc0fbcfdbc, and repeatedly sending 05bcbcbc87bcbcbc80bcbcbc1cbcbcbc. There was no disperr or notintable.

It looks like the initialization process stuck at some phase.

 

regards

 

Xiang Chao

 

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Xilinx Employee
Xilinx Employee
4,704 Views
Registered: ‎02-06-2013

Re: SRIO link problem

Hi

 

Does the link partner has loopback options and is it able to link up with itself.

 

You can use the far end loopback options in the core to make sure the data is fine on the TX and RX if Link partner is able to link up with loopback options including the end to end path.

Regards,

Satish

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