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1keith1
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Registered: ‎02-17-2014

SRIO v2.2 - My first IP core

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Hi, I'm an undergrad and while I have basic verilog experience, I have never used an IP Core before nor have I touched most other functions in xilinx.

 

I've been assigned with the task of designing an SRIO v2.2 interface for a virtex 6, and i'm here to get some help along the way.


I have a few months to accomplish this and I need to get started. So far I have gotten the hardware evaluation license, and I know how to use the GUI, but I don't know how to proceed after generating the code. 

 

Please, I would appreciate any help you can give, I know I have left a lot of details out, I can fill those in later. If there is any tutorials I should check out let me know.

 

Right now I am having trouble when I load up ISE and try to create the Rapid io ip-core I get this message:

Untitled.png

Afterwards the GUI loads up fine but what does the message mean?

 

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kotir
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Registered: ‎02-03-2010

 

 

The gui says that you have only simulation license. tis means you can not implement the files that you core is generating with this license.

 

I would suggest you to go through the below documents

 

http://www.xilinx.com/support/documentation/ip_documentation/srio_gen2/v2_0/pg007_srio_gen2.pdf

 

Regards,

Koti Reddy

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kotir
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Registered: ‎02-03-2010

 

 

The gui says that you have only simulation license. tis means you can not implement the files that you core is generating with this license.

 

I would suggest you to go through the below documents

 

http://www.xilinx.com/support/documentation/ip_documentation/srio_gen2/v2_0/pg007_srio_gen2.pdf

 

Regards,

Koti Reddy

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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi,

 

In the initial post you have mentioned that you have a Hardware evaluation license for this core. But from the snapshot, it looks like tool is able to pick the design linking license alone (with which you wont be able to generate bitstream).

 

If you have a hardware evaluation license for this core then place it in C:/.Xilinx location and restart the ISE tool so that it picks up the license. Now regenerate the core and see if you see the same warning message.

 

If possible please post the license file and xinfo file here.

 

In order to generate xinfo, please follow the steps below:

• Run Xinfo.exe from start
menu start->Xilinx ISE design suite->Accessories->xinfo system checker. It takes some time to generate Xinfo file.
• Check the common folder in Xilinx ISE_DS folder for Xinfo file.

 

Thanks,

Deepika.

Thanks,
Deepika.
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1keith1
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Registered: ‎02-17-2014

Here's a screen of my licenses which I am using, I added them to xilinx through the get license option: 

Licenses.png

 

 

I looked in the .xilinx folder and three licenses are there (including the ISE license).

 

The IP cores have locks next to their names still:

IPcores.png

 

Oh and I think I found the problem, in xinfo under "Host ID matches" column SRIO licenses have "No". I have been using Xilinx on multiple computers, and I have generated multiple ISE licenses, well now I'm stuck trying to find the ISE license and the Host that matches. I think I'll just try to generate new ones.

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1keith1
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Registered: ‎02-17-2014

Ok, new license generated, now Host ID matches and it works without errors.

So what will I do once I run the GUI and generate the files, what is usually the next step?

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yenigal
Xilinx Employee
Xilinx Employee
10,136 Views
Registered: ‎02-06-2013

Hi

 

I suggest you to go through the PG007 to know more about this core and go through the example design section..

 

You can simulate or implement this example design which will give you clear understanding of the core functionality and about the packet transfers.

 

you can then generate the core and interface with other devices.

 

 

Regards,

Satish

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1keith1
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Registered: ‎02-17-2014

So now i'm trying to simulate the example ip core following the guidlines in the pg007 but I'm using ISE not Vivado and i'm using a virtex 6 for Gen 2.

 

Anyways, in order to add the example design in I had to first remove the core (.xco) and then add in the files in the example_design folder.

 

But When I try to run the simulation I get this message: 

 

Untitled.png


The core created a  gtx_wrapper_ver.xco but there is no .v file

 

checked flist.txt and it isn't  listed.

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1keith1
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Registered: ‎02-17-2014

Edit to above: Fixed it by following a guide I found in another post:

 

1) Generate Verilog srio_gen2_vx_5 core in standalone

2) Implement Core
3) Create ISE project targeting the same device
4) Select "Project" -> "Add Source..."
5) Point to the "example_design" directory that has been created in "srio_gen2_v1_52"
6) Highlight all the files except for "srio_sim.v" and select "Open"
7) Select "Project" -> "Add Source..."
8) Point to the "cfg_fabric" directory that has been created in "srio_gen2_v1_52"
9) Highlight "cfg_fabric.v" file and select "Open"
10) Select "Project" -> "Add Source..."
11) Point to the "chipscoope" directory that has been created in "srio_gen2_v1_52"
12) Highlight "chipscope_icon_k7.xco", "chipscope_ila_k7.xco" and "chipscope_vio_k7.xco" file and select "Open"
13) Select "Project" -> "Add Source..."
14) Point to the directory where the SRIO core has been generated.
15) Highlight "srio_gen2_v1_5.v" and "srio_gen2_v1_5_synth.v" files and select "Open"
16) Now in the ISE project the SRIO hierarchy will be in the design and all files will be added
17) Expand "Implementation" in the "Design" tab
18) Right click on "Translation" and select "Process Properties"
19) The "Translation Properties"window will open. You will notice there is no path selected in the "Macro Search Path"
20) Point the "Macro Search Path" to teh directory where the srio_gen2_v_5 core was generated.
21) Run "Synthesis" and "Implementation" and all will pass with no errors.

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1keith1
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Registered: ‎02-17-2014

When I run the example srio_sim in isim it runs very slow. It is taking about 10 minutes to complete a 40microsecond simulation, CPU usage isn't that high either. Is this normal?

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yenigal
Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Yes this is normal with SRIO core simulation.

Regards,

Satish

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