to establish the link between ADC (JESD Tx) and FPGA (JESD Rx) I need of SYNCINB signal in output of the FPGA and input ADC.This signal must be deactivated from FPGA when it detetctes k28.5 character otherwise the ADC stream out continuously this charcter, but I don't find the SYNCINB signal in the module JESD204B (sub. 1) Rx generated with ISE. Can I have a solution?
Once lanes see K28.5s deasserts SYNC~ and for subclass 1 SYSREF signal is distributed to all devices in a system. On assertion, the JESD204 receiver aligns its internal Local Multiframe Clock (LMFC) to the incoming SYSREF signal and deasserts SYNC~.
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