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chlwogns414
Participant
Participant
695 Views
Registered: ‎12-06-2018

Select core in 10G/25G ethernet subsystem

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I am trying to make 10G ethernet interface in my custom board. 

I made my design refer to ZCU102 reference design in wiki.xilinx.com

chlwogns414_1-1611623872359.png

https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet

 

I just change fifo depth and ps core applied to my custom board(XZCU5CG)

 

I am using 16 bit effective data width DDR. Can this affect when choosing select core in 10G/25G ethernet subsystem? 

Is select core bit related to DDR's effective data width?

such as Ethernet MAC + PCS/PMA 64bit or Ethernet MAC + PCS/PMA 32bit?

 

Thank you

 

 

 

 

 

 

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nanz
Moderator
Moderator
608 Views
Registered: ‎08-25-2009

Hi @chlwogns414 ,

The FIFO depth is recommended to be set at the max depth in order to avoid FIFO might overrun issue to avoid a stall. You will have to experiment and run your application on your board to validate.

What I mean for "select core" is that you may see different supported options based on what device you are targeting. This external FIFO is irrelevant to the IP configurations and functionalities. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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4 Replies
nanz
Moderator
Moderator
643 Views
Registered: ‎08-25-2009

Hi @chlwogns414 ,

Which fifo depth have you changed? I assume it's outside of xxv IP?

No, this does not affect the configuration of xxv core. The "select core" option is based on the device that you choose in Vivado. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
chlwogns414
Participant
Participant
640 Views
Registered: ‎12-06-2018

Hi @nanz

 

I changed axis_data_fifo depth. In ZCU102 reference design  depth is 32768. I changed depth to 8192.

 

Can you explain 'The "select core" option is based on the device that you choose in Vivado. ' more detailed?

 

Thank You

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nanz
Moderator
Moderator
609 Views
Registered: ‎08-25-2009

Hi @chlwogns414 ,

The FIFO depth is recommended to be set at the max depth in order to avoid FIFO might overrun issue to avoid a stall. You will have to experiment and run your application on your board to validate.

What I mean for "select core" is that you may see different supported options based on what device you are targeting. This external FIFO is irrelevant to the IP configurations and functionalities. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

joe306
Scholar
Scholar
296 Views
Registered: ‎12-07-2018

Hello, did you get things working? I'm trying to do the same on my custom board. Would you be willing to share your project or a view of the block design to help me connect things up?

Thank you

Joe

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