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kailassenan
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Registered: ‎01-22-2008

Serial RapidIO v5.5 Logicore: Lower limit depth of ireq_data during SWRITE on IREQ Interface

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Dear Xilinx experts,

 

I am using Serial RapidIO v5.5 Logicore with an user interface providing FIFO data of 64 bit width and depth of 1K. I am using SWRITE transaction to send all the ireq_data from user interface fifo to the IREQ Request port. From the core user guide srio_ug503.pdf, I understood that during SWRITE transaction, the initiator request port can receive upto 32 depth of ireq_data[0:63] in one SWRITE transaction as shown in the timing diagram in Remote Endpoint Access>Memory write>Writing with SWRITE Transaction (page 179, figure 4-13 of srio_ug503.pdf).

 

Can the user interface able to send single ireq_data to the initiator request port using SWRITE transaction? For the last ireq_data transaction I have single data available in the FIFO to be read by the initiator request port. Can I able to send this single data using SWRITE transaction without using NWRITE transaction with byte offset?

 

Thanks and Regards

Kailas Senan

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mmcguirk
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Registered: ‎08-02-2007

Hi Kailas-

      Yes, you can send an SWRITE with a single dword (64-bits). You will just present it on a single cycle with both sof and eof asserted. You can modify the example testbench to do this and look at the behavior on the IREQ interface.

 

-Michael

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mmcguirk
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4,043 Views
Registered: ‎08-02-2007

Hi Kailas-

      Yes, you can send an SWRITE with a single dword (64-bits). You will just present it on a single cycle with both sof and eof asserted. You can modify the example testbench to do this and look at the behavior on the IREQ interface.

 

-Michael

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kailassenan
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Registered: ‎01-22-2008

Dear Michael,

 

Thank you for your reply. I will check this behavior.

 

Regards

Kailas Senan

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