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Registered: ‎09-04-2011

Set INERTIAL_DELAY in IIC module ...



When using Xilinx IIC core in master mode (to write data to external device), my written data get erroneous. I think I can solve this by using the internal delay configuration (C_SCL_INERTIAL_DELAY, C_SDA_INERTIAL_DELAY).


Regarding this case, how should I set these delay parameters?


1)      Should C_SCL_INERTIAL_DELAY and C_SDA_INERTIAL_DELAY be equal or different?

2)      If different what should be generally larger?

3)      What are the typical values? (i.e., 25,50,…)


Thank you.

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Xilinx Employee
Xilinx Employee
Registered: ‎07-21-2014

I think information given below could be useful to you


These parameters specify the number of SPLB_CLK cycles used to define the width of the pulse rejection. For
example, a 100 Mhz clock coupled with an C_SCL_INERTIAL_DELAY value of 5 gives 50 ns of pulse rejection. And,
incidentally, delays the signal internally by 50 ns.
Filtering SCL without filtering SDA can have potentially undesirable effects by causing SDA to change when SCL
is high resulting in false starts occurring.
Likewise, increasing the pulse rejection width for SDA beyond that for SCL may eliminate erroneous starts/stops
by increasing the SDA hold time. Although technically the Philips specification permits 0 ns of hold time, in practice
the sloppy signalling in IIC systems (caused by very large rise/fall times, due to high bus capacitance and high
pull-up resistance and/or the use of level translation mosfets) can result in failures due to the high speed sampling
of these analog signals.
In particular Virtex®-5 I/O are so fast that the slow signal rise time plus noise exceeding the input hysteresis can
result in phantom pulses internal to the circuit. The filters remove these quite effectively.
XPS IIC core provides 0 ns SDA hold time in master mode operation. If any IIC slave requires additional hold time
on the SDA from the core, this can be achieved by adding delay on SCL (C_SCL_INERTIAL_DELAY). For example,
for 100 Mhz PLB clock, to have 300 ns hold time, C_SCL_INERTIAL_DELAY parameter should be configured for a
integer value of 30. The parameter C_SDA_INERTIAL_DELAY can be set to 0 to 5 as per the required pulse


For more information please refer-


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