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Visitor
Visitor
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Registered: ‎03-28-2020

Signal 'MDIO_GEM_mdio_i' unavailable when instantiating GMII to RGMII core at ZYNQ PL, why?

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I create the block design, add GMII to RGMII IP named 'rgmii_eth', make external ports.

A BUG error show 'MDIO_GEM' bus signal 'MDIO_GEM_mdio_i' is not available. If (1) create HDL wrapper, or (2) save this block design to compile, or (3) validated this block design.

I believe that Xilinx is fully support a block design module "BD" to HDL instantiated.

 

I try to fan out 'MDIO_GEM' bus port through separated signals as this. It seems that the previous error is gone.

But the clock input 'gmii_clk_125m_in' has multi-drive error:

[DRC MDRV-1] Multiple Driver Nets: Net mmcm_0_inst/clk_wiz_0/inst/clk_out2 has multiple drivers: eth0_rgmii_eth_inst/gmii_to_rgmii_0/U0/i_bufgmux_gmii_clk/O, and mmcm_0_inst/clk_wiz_0/inst/clkout2_buf/O.

Why this input port has a output drive conflict with MMCM BUFG clock?

 

 

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @Adrianer ,

This is not the expected design flow. GMII2RGMII is used with Zynq/MPSoC device and supposed to be used in IPI. The interfaces should be hooked up with Zynq EMIO GMII interface and I do not understand why you want to instantiate it like this and where you plan to instantiate this IPI core? Why do you not use the IPI design flow but verilog instantiation?

Please try with Zynq GEM and see if you see any issues.

 

"Don't forget to reply, kudo and accept as solution."

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @Adrianer ,

I am not exactly sure what you are trying to do? Why are you not connecting GEM MDIO interface directly with GMII2RGMII core? And why the clocking is not connected to GEM GMII interface? It seems you are only trying to generate GMII2RGMII in BD and validate it? 

 

"Don't forget to reply, kudo and accept as solution."
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Visitor
Visitor
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Registered: ‎03-28-2020

I did instantiated GMII2RGMII block module to TOP verilog file. Not so many 'only try', step by step, it has error every step, validate error, compile error, confilict error. I has update to install version 2019.2 with vitis, but the same.

Or you try it for test, I don't know it you will get the same result.

rgmii_eth eth0_rgmii_eth_inst(
    // MDIO from CFG
    .mdio_gem_mdc(eth0_cfg_mdc),
    .mdio_gem_i (eth0_cfg_mdio_i),
    .mdio_gem_o (eth0_cfg_mdio_o),
    .mdio_gem_t (eth0_cfg_mdio_t),
    // MDIO to PHY
    .MDIO_PHY_mdc (eth0_phy_mdc),
    .MDIO_PHY_mdio_i (eth0_phy_mdio_i),
    .MDIO_PHY_mdio_o (eth0_phy_mdio_o),
    .MDIO_PHY_mdio_t (eth0_phy_mdio_t),
    
    // Tri-Speed clocks
    .ref_clk_in(eth0_clk_200MHz), // ref clock input
    .gmii_clk_125m_in (eth0_clk_125MHz),
    .gmii_clk_25m_in (eth0_clk_25MHz),
    .gmii_clk_2_5m_in (eth0_clk_2d5MHz),
    .mmcm_locked_in(eth0_clk_locked),
    
    // TX RX Reset
    .rx_reset(~reset_n),
    .tx_reset(~reset_n),
    
    // HALF DUPLEX status
    .GMII_col(),// output
    .GMII_crs (), // output
    
    // GMII RX to MAC
    .GMII_rx_clk (eth0_rx_clk),
    .GMII_rx_dv (eth0_rx_dv),
    .GMII_rx_er (eth0_rx_er),
    .GMII_rxd (eth0_rx_d),
    
    // GMII TX from MAC
    .GMII_tx_clk (eth0_tx_clk),
    .GMII_tx_en (eth0_tx_en),
    .GMII_tx_er (eth0_tx_er),
    .GMII_txd (eth0_tx_d),
    
    // RGMII RX from PHY
    .RGMII_rd (eth0_rxd),
    .RGMII_rx_ctl (eth0_rxdv),
    .RGMII_rxc (eth0_rxck),
    
    // RGMII TX to PHY
    .RGMII_td (eth0_txd),
    .RGMII_tx_ctl (eth0_txen),
    .RGMII_txc (eth0_txck),
 
    // Status from MDIO monitor
    .clock_speed (), // output, 00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: reserved
    .speed_mode (), // output, 00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: reserved
    .duplex_status (), // Full duplex active high
    .link_status () // active high
);

 

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Highlighted
Visitor
Visitor
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Registered: ‎03-28-2020

@Moderator,
Thank you for your help, but you may have some misunderstandings.
I have one GigE RGMII Ethernet Port at PS, but I also have two RGMII ports at PL to implement High speed Ethernt Data Exchange from PL to PL without PS Involved.
Some reference design actually use PS EMIO to auto Integrate this CORE, but I want use it at PL logic.

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Visitor
Visitor
307 Views
Registered: ‎03-28-2020

@Moderator, thank you for your help, but you may have some misunderstandings. I have one GigE RGMII Ethernet Port at PS, but I also have two RGMII ports at PL to implement High speed Ethernt Data Exchange from PL to PL without PS Involved. Some reference design actually use PS EMIO to auto Integrate this CORE, but I want use it at PL logic.

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Highlighted
Moderator
Moderator
329 Views
Registered: ‎08-25-2009

Hi @Adrianer ,

This is not the expected design flow. GMII2RGMII is used with Zynq/MPSoC device and supposed to be used in IPI. The interfaces should be hooked up with Zynq EMIO GMII interface and I do not understand why you want to instantiate it like this and where you plan to instantiate this IPI core? Why do you not use the IPI design flow but verilog instantiation?

Please try with Zynq GEM and see if you see any issues.

 

"Don't forget to reply, kudo and accept as solution."

View solution in original post

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Highlighted
Visitor
Visitor
307 Views
Registered: ‎03-28-2020

I check that this core is dedicated for soc EMIO GEM to PHY rgmii interface, OK, thank you for your help, I will implement this requirement through SelectIO, Thanks! 

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