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Adventurer
Adventurer
357 Views
Registered: ‎03-31-2017

Simplex Aurora simulation not initialising

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I've inherited an untested 8B10B Aurora receiver design, and I'm trying to simulate it, without success. The setup is very simple - V7, one 32-bit lane, 6.25G line rate, 156.25M refclk, 100M init_clk, Rx-only simplex, no flow control, timer back-channel.

The problem is that the Rx lane comes up, but not the channel. I'm simulating only the core netlists produced by Vivado, so I'm not compiling anything from the example design, with the exception of the 'partner' transmitter netlist. I've tried a number of different things, which all produce exactly the same result. I'm using two different models for the testbench transmitter:

  1. I generated an equivalent Tx-only simplex core, and I've used the VHDL and Verilog netlists as the transmitter in the testbench
  2. Vivado generates a netlist for the 'partner' transmitter when the receiver Aurora core is generated, and I've tried both the VHDL and Verilog versions

So the TB includes one of these two transmitter netlists, and the netlist for the receiver core itself.

I'm following the power-on sequence on p57 of PG046. This is what the sim is showing:

  1. Tx GT_RESET off at 200ns
  2. Rx GT_RESET off at 400ns
  3. Rx RESET off at 600ns
  4. Tx RESET off at 620ns
  5. Tx PLL locks at ~36us
  6. Tx and Rx USER_CLK start at about 36.7us
  7. Tx completes reset at about 38.5us
  8. Rx completes reset, and the Rx lane comes up, at about 96us

Nothing else happens (before 500us, anyway). The Tx lane doesn't come up, and neither the Tx nor the Rx channels come up. There are no obvious issues when checking the waveform displays for either the Tx or Rx.

Any ideas on what might be going wrong here? The setup is so simple that I'm guessing that it must have something to do with the reset sequencing, but I can't see what. Thanks.

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Adventurer
Adventurer
306 Views
Registered: ‎03-31-2017

Re: Simplex Aurora simulation not initialising

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I've managed to sort this out:

  1. The actual power-on sequence seems to be pretty much irrelevant. I'm currently using the one from the Coregen-generated testbench, which bears no relationship whatever to the one recommended in PG046: start with both GT_RESETs off, both RESETs on; set both GT_RESETs at about 100ns; clear both RESETs at about 200ns; clear the Rx GT_RESET at about 205ns; clear the Tx GT_RESET at about 740ns. But - note that the Coregen TB does not work. Maybe it did work once, with these timings. Or maybe it didn't.
  2. In some circumstances you will need the DRP clock running to carry out a reset; see AR#64091, #53779, #53561. This doesn't seem to be necessary in my specific case (this is a V7 GTH, but RXOUT_DIV is 1), but I have the clocks running just in case
  3. #64091 says that simulation has to run for 1.3ms. I'n now finding that all channels come up before 1.1ms, which is about 45 minutes of runtime.

So, in short, 45 minutes of runtime just to initialise the channels, before you can start your test.

The Coregen-generated TB is, to be frank, completely useless. It couldn't possibly work - it instantiates only the 38 files of the Rx core, and nothing else, and then runs for ever, doing nothing with unknown inputs and no stimulus. I've only run the Riviera code; maybe something else does work.

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Adventurer
Adventurer
307 Views
Registered: ‎03-31-2017

Re: Simplex Aurora simulation not initialising

Jump to solution

I've managed to sort this out:

  1. The actual power-on sequence seems to be pretty much irrelevant. I'm currently using the one from the Coregen-generated testbench, which bears no relationship whatever to the one recommended in PG046: start with both GT_RESETs off, both RESETs on; set both GT_RESETs at about 100ns; clear both RESETs at about 200ns; clear the Rx GT_RESET at about 205ns; clear the Tx GT_RESET at about 740ns. But - note that the Coregen TB does not work. Maybe it did work once, with these timings. Or maybe it didn't.
  2. In some circumstances you will need the DRP clock running to carry out a reset; see AR#64091, #53779, #53561. This doesn't seem to be necessary in my specific case (this is a V7 GTH, but RXOUT_DIV is 1), but I have the clocks running just in case
  3. #64091 says that simulation has to run for 1.3ms. I'n now finding that all channels come up before 1.1ms, which is about 45 minutes of runtime.

So, in short, 45 minutes of runtime just to initialise the channels, before you can start your test.

The Coregen-generated TB is, to be frank, completely useless. It couldn't possibly work - it instantiates only the 38 files of the Rx core, and nothing else, and then runs for ever, doing nothing with unknown inputs and no stimulus. I've only run the Riviera code; maybe something else does work.

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