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Observer yogesh_tc
Observer
9,327 Views
Registered: ‎10-18-2007

Simulation Results of 10GEMAC (v 8.2) and XAUI (v7.2)

Try out simulating functional Model of 10GEMAC (v 8.2) and XAUI (v7.2) cores.

Though the simulation completes normally.

Below message will be displayed on the Modelsim transcript window.

 

 ** Failure: Simulation Stopped
# Break in Module testbench at ../demo_tb.v line 1040

 

What does "failure" here means.............

is this made to display purposefully  or an mistake.

when I just looked in to demo_tb.v

(test bench  file inside the........ten_gig_eth_mac_v8_2\coregen\ten_gig_eth_mac_v8_2\simulation)

this is HDL description I found

 

initial
     begin
        fork: sim_in_progress
          @(posedge simulation_finished) disable sim_in_progress;
           #10000000                     disable sim_in_progress;
        join
        if (simulation_finished)
          $display("** Failure: Simulation Stopped");
        else
          $display("** Failure: ERROR: Testbench timed out");         
        $stop;
     end // initial begin

 

 

same kind of statement is there in XAUI (v7.2) test bench tooo....

ny body teach what failure here means !!!!!!!!!!

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2 Replies
Observer kal-el
Observer
9,316 Views
Registered: ‎08-02-2007

Re: Simulation Results of 10GEMAC (v 8.2) and XAUI (v7.2)

Hi yogesh_tc,

The "failure" you are seeing in the ModelSim simulation is not actually a failure of the simulation to do what is expected.  It's really just a selection for severity level of a message for ModelSim, and in this case the message uses a severity level of "failure" to indicate the simulation has been stopped after a successful run.

-Kal-El
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Observer yogesh_tc
Observer
9,298 Views
Registered: ‎10-18-2007

Re: Simulation Results of 10GEMAC (v 8.2) and XAUI (v7.2)

Hi Kal-El,
 
Thank you I got the point..
 

 
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