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ftamulonis
Visitor
Visitor
6,719 Views
Registered: ‎10-22-2013

Spacewire Implementation on XIlinx TEMAC 5.2

Hi Everyone,

 

I am using a SPARTAN-6 FPGA in on the SP605 Development board. I am using the TEMAC IP core version 5.2 to take Spacewire Data, send it through the MAC, and have it pop up on Wireshark. I am using the example design and a base so that none of the important features are left out. Currently I have data flowing from the spacewire source to the board. In order to make sure that it is entering the program I probed the signal tx_axis_fifo_tdata. I found that in fact the data is entering the program. But that is where it ends. If everying went right Wireshark should be showing 32 byte packets every second.

 

As some background, the example design comes with a pattern generator and address swapping module. In the data sheet UG777 and DS818, it says that this can be removed so that user data can be used. I have done this with sucess.

 

So to recap:  Using SPARTAN-6 on the SP605 Development Board

                        Trying to connect Spacewire Data to the MAC so that it can be transmitted by an Ethernet Cable

                        I have removed the pattern generator and address Swapping module's

                        No Spacewire data is appearing wireshark.

 

 

Any thoughts would be great. I believe it is something in the program probably in the axi_stream interface.

 

 

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yenigal
Xilinx Employee
Xilinx Employee
6,700 Views
Registered: ‎02-06-2013

Hi

 

What MAC interface are  you using to connect to the PC.

 

Does the link between the PC and the card is up.

 

Check if the clocks and reset to the core are fine.

 

Also  go through the Hardware debugging section of the below pdf.

 

http://www.xilinx.com/support/documentation/ip_documentation/tri_mode_eth_mac/v5_4/pg051-tri-mode-eth-mac.pdf

Regards,

Satish

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ftamulonis
Visitor
Visitor
6,661 Views
Registered: ‎10-22-2013

Hi Satish,

 

I believe the example deisgn comes with AXI-lite interface. 

 

After thinking about it a little I am going to try to send the data through the packet generator since that is the only I changed in the program. My thinking is that if I can connect the external data sources to the pattern generator data signals then the whole example design is less effected. 

 

Can I do this? Correct me if I am wrong. I am now reading on how the pattern gereator works to see what signals to connect to. 

 

 

Thank you for the user guide again it was helpful. 

 

 

 

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ftamulonis
Visitor
Visitor
6,656 Views
Registered: ‎10-22-2013

Wait, I think the interface is actually AXI4
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