Speed up simulation of GTP core in Artix 7 (Vivado)

[richterfhg]

Is there a possibility to speed up the simulation of the Artix GTP Core? Even in a simple loop test bench, the RX_RESET_DONE signal rises after 1.6ms and the simulation with ModelSim PE or XSim takes 45 min until this event. Setting the WRAPPER_SIM_GTRESET_SPEEDUP attribute on the common component does not speedup the simulation. In the ISE core 2.7 the simulation is much faster, the RX_RESET_DONE comes up after 150us.

[smarell]

Hi,

This is a known issue. The attribute SIM_RESET_SPEEDUP needed to be set to FALSE for production silicon reset requirements.

A change request was already filed to improve the simulation time.

You can see a slight improvement in the simulation time in 2014.1.

Regards,
Krishna

[dsammel]

Hi Krishna,

Using 2014.1, I changed the following attributes in the example design before simulating it:

• GTPE2_COMMON block: changed SIM_RESET_SPEEDUP from "FALSE" to "TRUE"
• GTPE2_CHANNEL block: changed SIM_RESET_SPEEDUP from "FALSE" to "TRUE"

The example design test bench failed after changing these to "TRUE" (it passed when they were both set to "FALSE" but it took a long time as richterfhg said). Is there any way I can work around this in 2014.1 so my simulations don't take so long, or do I have no choice but to wait for the change request to be implemented?

Thanks,

Dave

[smarell]

Hi Dave,

Using the simulators like questasim/modelsim can be a workaround. The overall time for simulation is less in these simulators when compared to xsim.

Regards,
Krishna

[venkata]

Try using VIVADO 2014.1 tool. startup time for library compilation has been improved dramatically with this version.

[richterfhg]

This is also no option. Even the 14.1 Viavado after finishing compile takes about one hour to simulate a simple GTP loop design until the RX_DONE event. ModelSim takes 45 minutes. This is completely unusable and I ported back my design to ISE 14.7

[richterfhg]

Is this simulation issue fixed in Vivado 14.2?

[dsammel]

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At ‎05-13-2014 03:11 AM, @smarell wrote:

Hi,

This is a known issue. The attribute SIM_RESET_SPEEDUP needed to be set to FALSE for production silicon reset requirements.

A change request was already filed to improve the simulation time.

You can see a slight improvement in the simulation time in 2014.1.

Regards,
Krishna

---

Hello again,

I am still seeing forum posts concerning the extremely long GTP simulation time. Could a Xilinx employee please 1) provide the number of the change request that Krishna mentioned (see quote above) and 2) confirm whether or not this CR has been scheduled? Thanks in advance.

Best regards,

Dave

[richterfhg]

In 2015.1 the simulation time of Artix GTP is still extremely long until release reset done. It connot be used for any simulation! Please fix this very old bug!

[woko]

(I know this is an old thread, but I think it needs to be brought up again.)

This issue is even true for Vivado 2015.2 (Aurora v11)!

The simulation time (for an Aurora design on Artix) around 1 hour is absolutely unacceptable when compared to seconds/minutes when compared to an Kintex-targetted design.

Is there any user, who has mentioned improvements with 2015.4 or even 2016.1 ?

Thank you,

[venkata]

The requirement to set SIM_RESET_SPEEDUP to FALSE is still valid. You can try to bypass the circuit implementing the reset sequence in figure 2-19 for "Simulation only" purpose and set SIM_RESET_SPEEDUP to TRUE.

The circuit can be found in <component_name>_gt.v[hd] file.

[woko]

---

@smarell wrote:

A change request was already filed to improve the simulation time.

---

Hi,

is there a chance, that this change will reach us some time?

Ok, the "channel_up" signal comes high after around 1ms of simulation time, which needs around 30mins to simulate on my system (I've got a pretty fast PC, btw).

Changing the "SIM_RESET_SPEEDUP" from true to false or vice versa doesn't change the simulation time for me.

It seems to me, that we have to live with this behavior.

Greetings,

[richterfhg]

There is no real solution. My workaround is simulating the GTP based designs in ModelSim with IP Cores build bei ISE. Of course this only works for 100T/200T. But with 16 GTPs in one design even this is very slow, I guess it comes from encrypted verilog models. So I wrote a simple fake module for GTP channels only for simulation. As I do not use AURORA or SATA or such protocols, this works OK for me. Simulating VIVADO models generelly is the hell.

[venkata]

Just changing the SIM_RESET_SPEEDUP parameter does not help. You need to bypass the circuit which implements the reset guidance for production silicon.