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Visitor radu
Visitor
240 Views
Registered: ‎06-16-2018

Start of Packet/Frame signal in "Timestamp Capture" IP block ( MAC 10/25G)

I need to use the signal internal to the "Tiemstamp Capture" block which is latching the  user generated ctl_rx_systemtimerin[80-1:0] ( and respectively tx_ptp_tstamp_out[79:0]  ) signal.  The signal is related to a Start of Packet (SOP) or a Start of Frame (SoF) at SERDES. 

Reference:  Fig 3-8, 3-9 , 3-10, 3-7  1G/10G/25G Switching Ethernet Subsystem v2.0 54   PG292 April 4, 2018

I would appreciate if anybody can indicate how  I can have this signal made available for my design logic.

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Moderator
Moderator
162 Views
Registered: ‎08-25-2009

Re: Start of Packet/Frame signal in "Timestamp Capture" IP block ( MAC 10/25G)

Hi @radu ,

Only 1G/10G MAC and PCS 32-bit is supported with tampstaming. There is a table on page6 of PG292 for that. Once the timestamping is enabled, you should see the signals on the block.

PTP.JPG

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Visitor radu
Visitor
124 Views
Registered: ‎06-16-2018

Re: Start of Packet/Frame signal in "Timestamp Capture" IP block ( MAC 10/25G)

Dear Nanz,

Thank you for the answer. Luckily I do not need IEEE 1588. I just need the Start of Packet (SOP) timed with the Serdes Clock (same time domain).  From what it is alluded in the note it appears that the IP contortions between the two time domains of the framing and gear box, though it is uncelar why it brakes the synchronicity at such an early stage of the pipe. I only wish, if possible, to configure somehow the IP and get an SOP within ( or clocked buy) serders Rx_clk.

 As a side note, it appears that latest revisions of 10G/25G High Speed Ethernet has expanded IEEE 1588 functionality for 25G (v3.0 7 PG210 May 22, 2019), if this would be of any help.

Regards,

Radu

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Moderator
Moderator
88 Views
Registered: ‎08-25-2009

Re: Start of Packet/Frame signal in "Timestamp Capture" IP block ( MAC 10/25G)

Hi @radu ,

I think you can enable 1588 in the core but you do not neccesaily need to use it.

But once it's enabled, you may have extra logics added to your design.

 

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