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a4speaker
Explorer
Explorer
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Registered: ‎06-19-2014

[Synth 8-5535] and [Opt 31-38] errors

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I am using a design including aurora example design and my own logic on KC705. Vivado version is 2015.2.

 

When I implemented design, It gave me error

 

[Opt 31-38] IBUFDS_GTE2 aurora_module/IBUFDS_GTE2_CLK1 I pin is connected directly to a top-level port. An IBUF must be inserted in between the port and the IBUFDS_GT

 

When I inserted IBUF as shown in attached figure, it gave me error in synthesis

 

[Synth 8-5535] port <gtx_clk_125_p> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
Port I of instance \aurora_module/IBUF_clk_125_p (IBUF) in module <mydesign_top>

 

vivado is not allowing me to add or remove IBUFs. What is the proper way to remove these errors.

 

My clocking scheme is that onboard 125 MHz clock is going to aurora example design and same clock is going in a MMCM which is generating different clocks for my own logic.

aurora_1.png
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vemulad
Xilinx Employee
Xilinx Employee
15,233 Views
Registered: ‎09-20-2012

Hi @a4speaker

 

As mentioned in AR http://www.xilinx.com/support/answers/53920.html you can drive IBUFDS_GTE2 output to BUFG/BUFH which can then drive MMCM.

 

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
8,847 Views
Registered: ‎09-20-2012

Hi @a4speaker

 

From the screenshot and the warning message it looks like the ports gtx_clk_125_p/n are going to IBUF as well as some other logic. Double click on the dotted line which is connected to the port in schematic and it will show you the other loads. 

 

Instead of driving the other loads from ports you can drive them from output of IBUFDS_GTE2. 

Thanks,
Deepika.
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a4speaker
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Registered: ‎06-19-2014

Thanks for your reply Deepika. Probably you havn't read the last sentence of my post. 

 

I mentioned that 125 MHz clock from source is driving aurora as well my own logic. This clock goes to an MMCM which is generating 3 clocks for my own logic.

 

Is this aproach which is causing problems? If I want to generate 3 more clocks from this 125 MHz clock, what should be aproach to do this?

 Can I use MMCM after IBUFDS_GTE2 ?

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vemulad
Xilinx Employee
Xilinx Employee
15,234 Views
Registered: ‎09-20-2012

Hi @a4speaker

 

As mentioned in AR http://www.xilinx.com/support/answers/53920.html you can drive IBUFDS_GTE2 output to BUFG/BUFH which can then drive MMCM.

 

Thanks,
Deepika.
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View solution in original post

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