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Adventurer
Adventurer
1,459 Views
Registered: ‎11-25-2016

TEMAC won't send data

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Hi, I try to send data from FPGA to PC using Ethernet. I used a data generator which generate cyclic data 01 to 04 and send them to TEMAC (myip IP in attached screenshot). my design works well in post synthesis and post implementation functional simulation but I'm not receiving any data in the PC (I'm using wireshark). I used 2 ILA IP to check my design. the first ILA (which checks data from generator to TEMAC) works well but the second one (which is going to check mii_tx) give me zero value. Any Idea what is wrong and how to fix it?

Capture.PNG
2.PNG
ila1.PNG
ila2.PNG
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Adventurer
Adventurer
1,967 Views
Registered: ‎11-25-2016

Re: TEMAC won't send data

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Hi Yenigal

Thanks for reply, I just solved it. The problem was axi_s_tlast which was low all the time. Small thing which I didn't realize.

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Moderator
Moderator
1,454 Views
Registered: ‎11-09-2017

Re: TEMAC won't send data

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Hi

 

Verify that the whole TEMAC block is not being held in reset. The whole block is held in reset if the main reset input or if a locked signal from an MMCM is Low.

 

Regards

Pratap

Regards
Pratap

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Scholar dpaul24
Scholar
1,425 Views
Registered: ‎08-07-2014

Re: TEMAC won't send data

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Hi @rezak3021,

 

You have not shown the complete set of mii_tx_* signals. Are you sure they are all good?

Note that mii_tx_clk is from PHY to FPGA, make sure the clock is coming in. If not please check out the PHY signals.

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Adventurer
Adventurer
1,405 Views
Registered: ‎11-25-2016

Re: TEMAC won't send data

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Yeah seems like that the problem is because of the clock from PHY. It stuck at one and I don't know why yet. I used DM9161AEP with 25Mhz oscillator and as far as I know, it should provide me the clock from one of it's pin.

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Adventurer
Adventurer
1,397 Views
Registered: ‎11-25-2016

Re: TEMAC won't send data

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I found out that DM9161AEP tx_clk will be latch input at reset. And if it latched to 1, then it ignore the whole transmit. But the datasheet says that the default value is 0, so it shouldn't be a problem but mine stuck at 1, which means the initial value in reset stage was 1. I don't know why :/

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Adventurer
Adventurer
1,378 Views
Registered: ‎11-25-2016

Re: TEMAC won't send data

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Now I'm receiving mii_tx_clk signal but now the problem is mii_tx_enable. In the attached screenshot, we can see that we have clok (first one), we don't have mii_tx_enable (second one) and we have tx_enable (last one). Any idea why I don't have mii_tx_enable? Also as you can see, post implementation simulation works fine :/

ila3.PNG
3.PNG
sim3.PNG
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Adventurer
Adventurer
1,360 Views
Registered: ‎11-25-2016

Re: TEMAC won't send data

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Help me please, I'm so frustrated

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Xilinx Employee
Xilinx Employee
1,355 Views
Registered: ‎02-06-2013

Re: TEMAC won't send data

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Hi

 

Below is the tx_enable logic generation.

 

So you need to look at the tx_mac_aclk which is derived from the PHY provided tx clock is free running and tx_reset_int is not held high.

 

  -- Create the transmitter clock enable
   txcesamplegen : process(tx_mac_aclk_int)
   begin
     if tx_mac_aclk_int'event and tx_mac_aclk_int = '1' then
       if tx_reset_int = '1' then
         tx_enable_int <= '0';
       else
         tx_enable_int <= not(tx_enable_int) after 1 ps;
       end if;
     end if;
   end process txcesamplegen;

 

If you look at the clocking and reset diagrams in PG051

 

Resets are synchronized to respective clock domains and the core should be held in reset until all the input clocks to the core are stable.

 

Check the polarity of the input resets is fine and make sure that they are held in reset(active low) until you see the phy provided tx and rx clock(as this is in MII mode) are stable.

Regards,

Satish

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Adventurer
Adventurer
1,968 Views
Registered: ‎11-25-2016

Re: TEMAC won't send data

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Hi Yenigal

Thanks for reply, I just solved it. The problem was axi_s_tlast which was low all the time. Small thing which I didn't realize.

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