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Participant toku1938
Participant
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Registered: ‎05-29-2018

The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Hi, 

I would like to ask whether I can use IEEE 1588 timestamp per packet using CMAC interface enabling AXIS.
My question overall is 
   Could IEEE 1588 timestamp interface be used to capture timestamp per packet (hopefully, both receiving and sending ) with AXIS interface?
The goal is to capture timestamps of each receiving and transporting packet. 

Environment is here.
  - Target Board: Xilinx VCU1525
  - Tool : Xilinx Vivado 2019.1
  - IP : CMAC (v2.6)
  - IP setting: CMAC interface is "AXIS" and "IEEE 1588" enabled (CAUI-4, 161.13MHz)

Regarding RX side, 
The IP manual says "This signal will be valid starting at thesame clock cycle during which the SOP is asserted for one of the LBUS segments." about RX_PTP_TSTAMP_OUT[79:0], which is ptp timestamp received.
So, this interface should be synced with LBUS interface. Since I use AXI Strema interface for CMAC, how should I synced this timestamp with AXIS interface ?
Since there is "LBUS to AXIS converter" between AXIS interface and LBUS interface, 
there should be some delays and alignment to shift the start of packet to the beginning of the interface.

TX side,
I conducted some implementation to observe the tx timestamp via ILA.
But, the timestamp seems a constant value.
I set the operation mode (refered as TX_PTP_1588OP_IN) to "No Operation". 
How can I set the interface for timestamp to be pushed on every packets?

Thank you a lot for your help in advance.

Best Regards,
toku1938

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Xilinx Employee
Xilinx Employee
284 Views
Registered: ‎09-05-2018

Re: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Hey @toku1938 ,

In the LBUS to AXI interface, the timestamp is passed through with the pack. So, the rx_ptp_tstamp_out signal for the packet will be asserted at the same time as the first rx_axis_tvalid signal for the packet. In other words, the signal is valid the first time rx_axis_tvalid goes high after rx_axis_tlast has gone low. In the attached picture, I've highlighted when the PTP timestamp is valid for the first three packets.

On the TX side, it sounds like you want to enable "two step operation". You can set TX_PTP_1588OP_IN to 2'b10 to enable this as shown in Table 3‐1: 1588v2 Port List and Descriptions of PG210.

Nicholas Moellers

Xilinx Worldwide Technical Support

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Is this "LBUS to AXIS converter" created by yourself?

CMAC only has the LBUS data interface and the other AXIS4-Lite interface for configurations (read/write IP registers)

https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_5/pg203-cmac-usplus.pdf

 

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Participant toku1938
Participant
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Registered: ‎05-29-2018

回复: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Dear, 

CMAC (>=v2.6) supports AXIS interface for network datapath. I think it is usefull to develop a system using AXIS rather than LBUS.
So, I would like to know how to sync PTP timestamp with AXIS.

Best Regards,
toku1938

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Xilinx Employee
Xilinx Employee
285 Views
Registered: ‎09-05-2018

Re: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Hey @toku1938 ,

In the LBUS to AXI interface, the timestamp is passed through with the pack. So, the rx_ptp_tstamp_out signal for the packet will be asserted at the same time as the first rx_axis_tvalid signal for the packet. In other words, the signal is valid the first time rx_axis_tvalid goes high after rx_axis_tlast has gone low. In the attached picture, I've highlighted when the PTP timestamp is valid for the first three packets.

On the TX side, it sounds like you want to enable "two step operation". You can set TX_PTP_1588OP_IN to 2'b10 to enable this as shown in Table 3‐1: 1588v2 Port List and Descriptions of PG210.

Nicholas Moellers

Xilinx Worldwide Technical Support

View solution in original post

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Participant toku1938
Participant
256 Views
Registered: ‎05-29-2018

Re: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Hi @nmoeller 

Thank you for the reply.

This is what I want to know.
You mean that RX timestamp (rx_ptp_tstamp_out ) is synced with AXI-S interface, right? (I worried about the delay between AXIS and LBUS might happen.)

Best Regards,
Yuta

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Xilinx Employee
Xilinx Employee
242 Views
Registered: ‎09-05-2018

Re: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Hey @toku1938,

Yes, it is synced to the axi interface. Sample the value from rx_ptp_tstamp_out when axi asserts tvalid for the first time and each time tvalid is asserted after tlast is asserted.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Participant toku1938
Participant
230 Views
Registered: ‎05-29-2018

Re: The interface of IEEE 1588 timestamp on CMAC for using per packet to get each timestamp

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Hi @nmoeller 

Thank you very much for your kind help.

Best Regards,
toku1938

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