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Explorer
Explorer
5,629 Views
Registered: ‎10-25-2012

The system reset and GT reset for the Aurora V9.1 simplex streaming timer mode

In my design, I use the Aurora IP. The Aurora is configured to work in the Simplex mode, the interface is streaming, the back channel is timer. I read the PG046, but the section about reset is confusing. I have following questions:

1. The PG046 doesn't talk too much about GT reset. When should I do the GT reset?

 

2. At the beginning, I want to bring up TX and RX. In page 62, The document said "

RX_SYSTEM_RESET is deasserted (or) released after TX_SYSTEM_RESET is deasserted.
This ensures that the transceiver in Simplex-TX core starts transmitting initialization
data much earlier and it will enhance the likelihood of the Simplex-RX core aligning to
correct data sequence." This doesn't make sense. In the timer mode, TX and RX are blind with each other. Why not deassert RX before TX then RX is ready to receive the initialization data?

 

3. What reset I should do if during the transmit, TX or RX confront hard_err to make the channel down? Do I need to assert GT reset? How should I assert TX and RX system resets? Is there any coordinate between them?

 

4. In page 62, it states "RX_CHANNEL_UP is asserted before TX_CHANNEL_UP assertion. This condition must be

satisfied by the Simplex-RX core and simplex timer parameters (C_ALIGNED_TIMER,
C_BONDED_TIMER and C_VERIFY_TIMER) in Simplex-TX core needs to be adjusted to
meet this criteria."

I checked the Aurora core, there are only C_ALIGNED_TIMER and C_VERIFY_TIMER, there is C_BONDED_TIMER . Both of them are just two13bits number, how can I adjust them?

 

Thanks in advanced.

2 Replies
Visitor lakata
Visitor
5,337 Views
Registered: ‎05-08-2014

Re: The system reset and GT reset for the Aurora V9.1 simplex streaming timer mode

I'm looking for the answer to this question as well, but it 1/2 year old now.
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Moderator
Moderator
5,332 Views
Registered: ‎02-16-2010

Re: The system reset and GT reset for the Aurora V9.1 simplex streaming timer mode

GT_RESET at the Rx needs to be done when there is valid data present on the serial lines. This applies to all transceivers.

With Simplex cores using timer as back channel mode, the major criteria is to ensure the following
"RX_CHANNEL_UP is asserted before TX_CHANNEL_UP assertion. This condition must be

satisfied by the Simplex-RX core and simplex timer parameters (C_ALIGNED_TIMER,
C_BONDED_TIMER and C_VERIFY_TIMER) in Simplex-TX core needs to be adjusted to
meet this criteria."

Since these attributes control the counters..you could calculate the time it takes to expire these counters based on the clock frequency and width of the counters.

To adjust the counters, you will need to know the latency between de-assertion of Rx_system_reset and Tx_system_reset.
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