04-17-2018 05:46 AM
Hi, at present,I debugging optical fiber communication based on FPGA，use aurora8b/10b_v5.3 .To the success of the simplex simplex and duplex duplex,but engineering needs FPGA_1 to FPGA_2 and FPGA_2 to FPGA_3 while each board has only one pair of LC interfaces,So there are some questions I'd like to ask,if two FPGA I choose duplex communication, can I use only one optical fiber（FPGA_2 receives data from FPGA_1 while communicating with FPGA_3）? or two simplex in a pair of LC interface, one receives a send（but Map has been making a mistake）?
04-17-2018 06:45 AM
Using a duplex link in FPGA_2 will not work. Two simplex links should work if the software will allow it.
04-17-2018 05:53 PM
Thank you for your reply，Before I try on FPGA_2 with two simplex(RX-only Simplex and TX-only Simplex),but error in map. presents the message:
ERROR:Place:1073 - Placer was unable to create RPM[GTP_RPMs] for the component
type GTP_DUAL for the following reason.
The reason for this issue:
Some of the logic associated with this structure is locked. This should cause
the rest of the logic to be locked.A problem was found at site
GTPA1_DUAL_X0Y0 where we must place GTP_DUAL
order to satisfy the relative placement requirements of this logic. GTP_DUAL
to already be placed there which makes this design unplaceable. The
following components are part of this structure:
Then I went to read UG, but I didn't find the answer.
04-25-2019 08:03 PM
hi @xietiantian ,
i believe and assume this issue might be due to shared logic resources ,The shared logic option in the Vivado IDE configures the core to include sharable resources such as the transceiver quad PLL (QPLL), the transceiver differential refclk buffer (IBUFDS_GTE2), and clocking and reset logic in the core or in the example design. When the include shared logic in core option is selected, all sharable resources are available to multiple instances of the core minimizing the amount of HDL modifications required while
retaining the flexibility to address more use cases.
can you throw some light on shared logic
04-25-2019 08:27 PM - edited 04-25-2019 08:27 PM
you need to put a simplex TX aurora and a simplex RX aurora in to a GT CHANNEL in FPGA #2.
Below is an example for your reference.