cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
1,099 Views
Registered: ‎04-09-2018

The use of aurora8b/10b

Hi, at present,I debugging optical fiber communication based on FPGA,use aurora8b/10b_v5.3 .To the success of the simplex simplex and duplex duplex,but engineering needs FPGA_1 to FPGA_2 and FPGA_2 to FPGA_3 while each board has only one pair of LC interfaces,So there are some questions I'd like to ask,if two FPGA I choose duplex communication, can I use only one optical fiber(FPGA_2 receives data from FPGA_1 while communicating with FPGA_3)? or two simplex in a pair of LC interface, one receives a send(but Map has been making a mistake)?
 

text.jpg
0 Kudos
Reply
4 Replies
Scholar
Scholar
1,076 Views
Registered: ‎03-28-2016

Using a duplex link in FPGA_2 will not work.  Two simplex links should work if the software will allow it.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
0 Kudos
Reply
Visitor
Visitor
1,064 Views
Registered: ‎04-09-2018

Thank you for your reply,Before I try on FPGA_2 with two simplex(RX-only Simplex and TX-only Simplex),but error in map. presents the message:

 

ERROR:Place:1073 - Placer was unable to create RPM[GTP_RPMs] for the component
U4_gtp_next/U3_aurora_v53_next/gtp_wrapper_i/GTP_TILE_INST/gtpa1_dual_i of
type GTP_DUAL for the following reason.
The reason for this issue:
Some of the logic associated with this structure is locked. This should cause
the rest of the logic to be locked.A problem was found at site
GTPA1_DUAL_X0Y0 where we must place GTP_DUAL
U4_gtp_next/U3_aurora_v53_next/gtp_wrapper_i/GTP_TILE_INST/gtpa1_dual_i in
order to satisfy the relative placement requirements of this logic. GTP_DUAL
U1_gtp_exdes/U3_aurora_v53/gtp_wrapper_i/GTP_TILE_INST/gtpa1_dual_i appears
to already be placed there which makes this design unplaceable. The
following components are part of this structure:

 

Then I went to read UG, but I didn't find the answer.

0 Kudos
Reply
Moderator
Moderator
500 Views
Registered: ‎05-02-2017

hi @xietiantian ,

 

i believe and assume this issue might be due to shared logic resources ,The shared logic option in the Vivado IDE configures the core to include sharable resources such as the transceiver quad PLL (QPLL), the transceiver differential refclk buffer (IBUFDS_GTE2), and clocking and reset logic in the core or in the example design. When the include shared logic in core option is selected, all sharable resources are available to multiple instances of the core minimizing the amount of HDL modifications required while
retaining the flexibility to address more use cases.

can you throw some light on shared logic

 

Regards
Chandra sekhar
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if solution provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Reply
Xilinx Employee
Xilinx Employee
493 Views
Registered: ‎08-07-2007

hi @xietiantian 

 

you need to put a simplex TX aurora and a simplex RX aurora in to a GT CHANNEL in FPGA #2.

Below is an example for your reference.

 

https://www.xilinx.com/support/answers/47672.html

 

Thanks,

Boris

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Reply