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Explorer
Explorer
3,749 Views
Registered: ‎04-01-2016

Timing failure on Aurora 64b/66b

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Hi everybody,

 

I have a few problems with the Aurora 64b/66b IP core. I already searched for solutions here on the board and I wonder that it seems that nobody has had the problem before.

 

So my timing analysis gives me many timing failures on the following clocks:

 

  • user_clk_i
  • sync_clk_i
  • RXOUTCLK

I included the following constraints in my xdc-file as provided by Xilinx IP Core Gen:

 

set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells  Toplevel/fpga2fpga_communication/framinginterface_inst/AuroraIF/inst/AuroraFraming_core_i/AuroraFraming_wrapper_i/AuroraFraming_multi_gt_i/AuroraFraming_gtx_inst/gtxe2_i]

set_false_path -to [get_pins -hier *data_fifo*/RST]
set_false_path -to [get_pins -hier *rxrecclk_bufg_i*/CE]

# Create clock constraint for TXOUTCLK from GT
create_clock -period 8.000	 [get_pins -hier -filter {name=~*AuroraFraming_wrapper_i*AuroraFraming_multi_gt_i*AuroraFraming_gtx_inst/gtxe2_i/TXOUTCLK}]

# Create clock constraint for RXOUTCLK from GT
create_clock -period 8.000	 [get_pins -hier -filter {name=~*AuroraFraming_wrapper_i*AuroraFraming_multi_gt_i*AuroraFraming_gtx_inst/gtxe2_i/RXOUTCLK}]

# below constraint is needed for core
set_false_path -to [get_pins -hier *AuroraFraming_cdc_to*/D]

set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}]

If you need more information do not hesitate to ask.

 

Kind regards

Sebastian

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1 Solution

Accepted Solutions
Explorer
Explorer
6,977 Views
Registered: ‎04-01-2016

Re: Timing failure on Aurora 64b/66b

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Hi,

 

thanks for your response. I think I now made it. It was due to the hierarchy. I applied the timing constraints but it seems to me that the hierarchy is case sensitive, is that true?

 

Now I have another question related to the MGT. My MGT is running on a different clock frequency as my main FPGA speed. Therefore I have to synchronize the data. Can you give me a good user guide or xapp which describes how to to that? My guess is with a dual ported RAM.

 

Kind regards

Sebastian

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3 Replies
Xilinx Employee
Xilinx Employee
3,731 Views
Registered: ‎02-14-2014

Re: Timing failure on Aurora 64b/66b

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Hello @sebastian_z,

 

Are you facing this problem with IP example design? If yes, can you share IP customization (.xci) file to reproduce the issue ?

You need to separately attach modified files, if you have changed some of the files from example design.

Regards,
Ashish
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Moderator
Moderator
3,725 Views
Registered: ‎02-16-2010

Re: Timing failure on Aurora 64b/66b

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Most of the constraints you mentioned are part of IP internal files. Are you not using .xci file in your project?

Whether there are any critical warnings on these constraints?
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Explorer
Explorer
6,978 Views
Registered: ‎04-01-2016

Re: Timing failure on Aurora 64b/66b

Jump to solution

Hi,

 

thanks for your response. I think I now made it. It was due to the hierarchy. I applied the timing constraints but it seems to me that the hierarchy is case sensitive, is that true?

 

Now I have another question related to the MGT. My MGT is running on a different clock frequency as my main FPGA speed. Therefore I have to synchronize the data. Can you give me a good user guide or xapp which describes how to to that? My guess is with a dual ported RAM.

 

Kind regards

Sebastian

0 Kudos