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Visitor m_kr
Registered: ‎02-01-2017

Timing issues with multiple PCS/PMA cores on UltraScale target device

Hi all,


I'm using four PCS/PMA cores in 10GBASE-KR Mode which are all in the same GT-QUAD on the UltraScale target device. I generated one core with included shared logic in core and the others with include shared logic in example design. The former core with included shared logic provides the clocks and control signals for the other cores as mentioned in the data sheet (PG068 Figure3-23).


However, the design failed to meet the timing requirements. The Problems are between dclk clock and rxoutclk_out and dclk and txoutclk_out.


The dclk clock is a freerunning clock and it is set to 156.25 MHz on each core. The same clock source is used for all dclk core clocks. This should be fine according to PG068


The Timing Issues occur on the reset_rx_done and reset_tx_done signal. These signals are used in different clock domains (dclk clock/rxoutclk_out) and (dclk/txoutclk_out).


But I have no clue why there are timing issues because the routing of the clocks and control signals are done like in Figure 3-23 PG068.

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