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Adventurer
Adventurer
2,048 Views
Registered: ‎08-30-2018

Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Hi,

 

I am working wothCicado 3017.3 targeting a zc706 board.

 

I am trying to write some data in the DDR3 of PL and then use AXI DMA (or CDMA, I am a liitlebit confused which one) to read that data from DDR3-PL and write into a Block RAM. My design proposal is like below. I have implemented and generated bitstream.

In this design, I write a datato DDR3-PL through PCIe and they try to transfer it to the BRAM via Zynq Processor in SDK.

I could write data to DDR3-PL via PCIe, but when I read the content of BRAM, it is not identical with datain DDR3-PL.

Can anyone help me to solve this issue? Thanks in advance for your support.

Best,

Daryon

 

ddr3pl_bram.png

 

22 Replies
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Voyager
Voyager
2,037 Views
Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

I'm struggling with the picture because even enlarged doesn't have resolution enough... but looks correct to me. 

So you read from the external DRAM via DMA, stream to the FIFO and the FIFO sends the data to the BRAM via the same DMA, then you check it out.

If that doesn't work I would first double check the DMA settings and addresses.

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm

Sorry for this inconvenience. Here is the uploaded PDF format of the schematic.'

Thanks again,

Daryon

 

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Adventurer
Adventurer
2,029 Views
Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm

 

So you read from the external DRAM via DMA, stream to the FIFO and the FIFO sends the data to the BRAM via the same DMA, then you check it out.

 

Does this procedure seem logic and correct in your opinion? May I do someting wrong with my schematic?

Thanks

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Yes, that procedure seems alright to me.

Just one thing to check out: you have (physically and implemented in your bd) both the PS DDR memory and the external SODIMM memory via the MIG... you are not writing to one then checking for the other, right?

The FIFO has the rst pin unconnected, probably doesn't matter, just in case...

If those quick checks don't improve things, I would have a look into the software, a 'standard' example should be reliable. Then, time to stick an ILA and have a look inside of the guts...

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm

Just one thing to check out: you have (physically and implemented in your bd) both the PS DDR memory and the external SODIMM memory via the MIG...

Yes, I did...

 

you are not writing to one then checking for the other, right?

No, not at all, I never touch the DDR_PS because its data width is 32-bits and it is not useful in my case.

 

The FIFO has the rst pin unconnected, probably doesn't matter, just in case...

I forgot to connect it, I'll do the connection

 

I would have a look into the software, a 'standard' example should be reliable.

Can ytouplease elaborate more on this hint? I also have in mind that if I would like to read data from DDR_PL (i.e. MIG) and send to the BRAM, the DDR_PL should be visible by Zynq Processing System, isn't it?

Also, I am using the poll_SG C code provided by Xilinx to test the functionality of this design in SDK which I do not know is the correct choice or not?!

 

Thanks in advance for your support.

 

Bests,

Daryon

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

On the last bit:

Any memory connected to the PS, either directly or through AXI is visible to the software, but not straight away.

I'm a bit suspicious when you say "I never touch the PS DDR" because that is the basic memory of the PS.

In SDK, if you right click on your project and select 'Generate Linker Scripts' a dialog will pop up with the memory distribution for your software. I think even if you have some memory physically connected, you can't address it from software unless it's mapped in the linker script.

This goes a bit beyond my knowledge, but I feel you have to add a data section (right half, 'Advanced' tab, in 'Data section' click 'Add section' and you should be able to see your other RAM. Name it '.extRam' for example. Then in software to have a variable physically there, for example:

<type> <variable> __attribute__ ((section (".extRam"))) ;

It is possible to specify the boundaries of sections, so if it matches your variable size then you have a "software equivalent" of a physical memory area. 

All of this is because even if you "read from the DDR_PL and write into the BRAM", you will still need to write some known data in the DDR_PL first.

The SG mode shouldn't make a difference in a simple one place to one place transfers. 

 

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm

 

Thanks for your explanation. Here is a snapshot of Generate Linker Script wizard. As it shows, the DDR3_PL (entitled mig_7series_ddr3pl_memaddr) is visible for the Zynq Processing System.

 

Screenshot from 2018-11-21 09-55-17.png

 

All of this is because even if you "read from the DDR_PL and write into the BRAM", you will still need to write some known data in the DDR_PL first.

Yes, it is right. Primarily I write some known data to DDR_PL via PCIe.

 

The SG mode shouldn't make a difference in a simple one place to one place transfers. 

Do you mean that the SG mode is redundant and can be disabled from AXI DMA settings?

 

Thanks for your support.

Bests,

Daryon

 

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Good. But I still think you need to go to the Advanced tab and set up a new section physically bound to the external DDR.

The SG mode can be disabled in the block configuration, but I don't expect that to be a problem.

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm,

 

Here is the snapshot of Advanced tab. It is seen that all the tasks are handled by PCIe/CTL0 which was set 256MB in my block design.

Should I define the external RAM in the 'Data Section Assignments' or elsewhere?

 

Thanks again,

data section.png

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

@johnvivm,

Please note that clicking on the Add Section button in Data Section Assignment does not show anything as shown in the snapshot below:

 

add section.png

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

You don't assign memory to sections, but sections to memory. Add a new section, name doesn't matter, type would be data, of course.

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Enter just a name 'extMem' or whatever, then you will have one more row in the list of sections, use the dropdown to select 'mig_7series_ddr_pl...'

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm

 

I did a step-by-step design verification in SDK but unfortunately there is a problem with Received packet. I seems that the AXI DMA does not operate and cannot fetch data from DDR3_PL although it has access to it.

 

Bests,

Daryon

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Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm,

 

After multiple trials and strives to solve this issue, I suspect that the AXI DMA will operate well if and only if one end of data transaction be inside the Zynq DDR_PS, otherwise transferring between two memories located in PL part (i.e., in my case from DDR3_PL to the BRAM) might not be possible with AXI DMA! I do not know!

 

Did you havany experience with this?

 

Thanks and Regards,

Daryon

 

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

I use the AXI DMA with external memories interfaced with MIG and streaming into consuming processes. Many people use it in many combinations (PS memory, PL external memory, PL internal memory). The PS external memory, if you think about it, is probably the most complex in terms of "things in the middle" for the interconnect inside the PS plus the interface to the external mem. It should be easier to interface other two types of memory. I have a principle: when something is looking like becoming impossible, something simple has been obviated. I'll have a look tonight at home.

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Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear folks,

 

Isn't there any other suggestion or experience about this issue? It seems impossible to transfer data from DDR3_PL to BRAM because unlike a dual-port BRAM, DDR3_PL does not have a common link back to DDR3_PL !

 

Any suggestion and help is in advance appreciated.

Bests,

Daryon

 

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

started a project about this on a similar board, hopefully helps. Had a PC problem yesterday, need to reinstall from fresh. Sh happens.

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm,

 

Thanks a lot for your care and support. Can you please share your design and SDK code with me whenever the issue with your PC is solved?

Thanks again,

Daryon

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Voyager
Voyager
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Registered: ‎08-16-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Of course I will. I do that because is relevant for my projects as well, don't think I'm an altruistic folk with 24 free hours a day :D :D.

I'm suspecting all the trick is in the software. Hardware is simpler, you need a big blunder (and normally obvious) for things not to work at all. With software just a subtlety makes that effect.

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Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Thanks @johnvivm. I understand you and your busy time as an engineer. I appreciate it. Meanwhile, if I fins any news in my trials, I will share it here with you :)

 

Thanks again,

Daryon

 

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @johnvivm,

 

UPDATE:

While I am trying to launch the SDK code even after defining MIG_7Series DDR3 as an .extRAM in Data Section of Linker Script, I get the following error message that prevents the program execution!

Screenshot from 2018-12-03 13-02-31.png

 

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Observer
Observer
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Registered: ‎02-23-2019

Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

Dear @daryon  and @johnvivm,

If I want to transfer the data from PL DDR to the BRAM, do I need to use the FIFO in between? can't I directly transfer the data without FIFO using the CDMA? how to configure the CDMA to access specific address blocks in the PL DDR? Once the data in the BRAM, I want to read this data to my logic and do some arthematic operations, apply fft and write back this data to PL DDR. Can please help me how to do this?

 

Thanks,

Msreddy

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