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jeevanreddymandali
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Registered: ‎11-03-2013

Transmission on 4 byte lane channel using aurora protocol

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Hi guys, I am doing a project in which I should transmit 192 bits but I am not getting my laneup and channel up. And what is the technique if I want to use 4 lanes as a single channel in my project.

Thank you.

Jeevan Reddy Mandali

jeevanreddymandali
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venkata
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Registered: ‎02-16-2010
how you are verifying the TX data is not present at the receiver?

I hope you are aware that there will be some latency to find the TXDATA at receiver.
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athandr
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Registered: ‎07-31-2012

Hi,

 

What version of Aurora Core are you using? Is it an 8b/10b or 64b/66b core?

Thanks,
Anirudh

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venkata
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Hi,

It seems the target bit width and number of lanes chosen does not match. To transmit 192 bit data with 4-byte data on each lane, you need 6-lane design. You are referring to a 4-lane design. Can you please review this to start with?

Please generate a 6-lane Aurora 8B10B design..
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jeevanreddymandali
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Hello, thanks for your time. My lane_up, channel_up are up now, this is by adding unisim libraries in lane_init_sim.vhd. How can we say that the target bit width and number of lanes chosen does not match. How to avoid this problem. But now i am facing another problem. I am integrating a 192 bit counter.vhd, fifo to aurora 1lane, 4 byte. The data from counter should be stored in fifo, come out from fifo in 32 bits 6 times and go to aurora. I have used loopbac="010" in my project, but i am unable to receive the transmitted data on the signal rx_d_i. If you want my simulation snapshots i will post them.

 

jeevanreddymandali
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jeevanreddymandali
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Registered: ‎11-03-2013
8b/10b v5.1. Hello, thanks for your time. My lane_up, channel_up are up now, this is by adding unisim libraries in lane_init_sim.vhd. How can we say that the target bit width and number of lanes chosen does not match. How to avoid this problem. But now i am facing another problem. I am integrating a 192 bit counter.vhd, fifo to aurora 1lane, 4 byte. The data from counter should be stored in fifo, come out from fifo in 32 bits 6 times and go to aurora. I have used loopbac="010" in my project, but i am unable to receive the transmitted data on the signal rx_d_i. If you want my simulation snapshots i will post them.
jeevanreddymandali
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jeevanreddymandali
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Hello, here are my simulation results and black box rtl view. Please take a look.

Thanks

snap1.pngsnap2.pngsnap3.pngsnap4.pngsnap5.pngrtl.png

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venkata
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Registered: ‎02-16-2010
if you are using the frame_check module from example design, can you let us know if you find any error count output asserted from this module?
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jeevanreddymandali
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I am not using frame_check module, there is no error_count output.
Regards,
jeevanreddymandali
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venkata
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Registered: ‎02-16-2010
how you are verifying the TX data is not present at the receiver?

I hope you are aware that there will be some latency to find the TXDATA at receiver.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

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