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Registered: ‎11-24-2019

Tri Mode Ethernet MAC not working


I am trying to simulate tri mode ethernet MAC (AXI 1G Ethernet subsystem v7.1, Vivado 2019.1 targeting Questasim simulator), and trying to do some loopback tests.
For this I am writing and reading MDIO registers. I am configuring Control (Register 0) and Loopback (Register 17) through AXI Lite interface.
I am transmitting data, however I do not see the data being looped back.

Following are my register configuretions-
Address Data
MDIO Setup -> 0x00000500 -> 0x00000071 (AXI clock = 250MHz, MDC clock = 2.5 MHz)

MDIO control writes -> 0x00000508 -> 0x00005140
0x00000504 -> 0x01004800

MDIO Loop reg writes -> 0x00000508 -> 0x00000001
0x00000504 -> 0x01114800

When I try to read back control and loopback registers I find that Loop back register
is not made high.

Control Register Reads -

Address Data
0x00000504 -> 0x1008800
0x0000050C -> 0x0015140 (Correct configured data)

0x00000504 -> 0x01118800
0x0000050C -> 0x00010000 (Incorrect configured data)

Please help

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1 Reply
Registered: ‎11-09-2017

Re: Tri Mode Ethernet MAC not working

Hi n.kiran@partner.samsung.com 

Infrastructure cores for AXI 1G Ethernet subsystem are TEMAC and 1G/2.5G Ethernet PCS/PMA, additional functionality is provided using the AXI Ethernet Buffer core.

Are you looking to loopback data at 1G/2.5G Ethernet PCS/PMA?

Loopback is not supported by the core when RxGmiiClksrc=RXOUTCLK.

- Xilinx core provides example design with test bench - loopback, right on .xci file and select open example design. You can simulate and can be use for your reference.

- 1G/2.5G Ethernet PCS/PMA also provides gt_loopback ports (internal loopback), enable transciever control and status configuring the IP.


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