cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
csommer
Observer
Observer
663 Views
Registered: ‎02-03-2021

Troubleshooting AXI Ethernet - Zynq - SGMII - Marvell PHY

Hi,

I am trying to setup SGMII ethernet with a Marvell 88E1512 through Axi-Ethernet 1G/2.5G 7.1 on a Zynq-7000.
The PHY is sitting on a custom board with its own 25 MHz clock, while another 125 MHz differential clock is linked to the Zynq.

Upon boot, I can see that:

csommer_0-1618437068885.png

When I run mii-tool -v -v eth1, the vendor ID corresponds to Xilinx PHY identifier (0x5d03), but I was expecting 0x5043 (Marvell 88E1512 identifier).
Is that normal?

csommer_2-1618437206833.png

How can I confirm that the MDIO link works fine and move-on to troubleshooting the SGMII link?

 

0 Kudos
12 Replies
nanz
Moderator
Moderator
618 Views
Registered: ‎08-25-2009

Hi @csommer ,

What does your DTS file look like? Is the Marvel PHY configured externally or you are using MDIO? 

It seems fine to me at this stage if your Marvel PHY is pre-configured. AXI Ethernet does include its own SGMII PHY if using it in SGMII mode. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
0 Kudos
csommer
Observer
Observer
572 Views
Registered: ‎02-03-2021

Hi @nanz ,

Thank you for the prompt reply.

Here is my DTS file (I am using 2018.2 for project compatibility reasons):

 

 

		axi_dma_eth11: dma@80400000 {
			#dma-cells = <0x1>;
			axistream-connected = <0xe>;
			axistream-control-connected = <0xe>;
			clock-names = "s_axi_lite_aclk";
			clocks = <0x1 0xf>;
			compatible = "xlnx,eth-dma";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <0xf>;
			interrupts = <0x5 0x2 0x4 0x2>;
			phandle = <0x10>;
			reg = <0x80400000 0x10000>;
			xlnx,include-dre;
		};

		axi_ethernet_11: ethernet@81000000 {
			axistream-connected = <0x10>;
			axistream-control-connected = <0x10>;
			clock-frequency = <0x5f5e100>;
			clock-names = "ref_clk";
			clocks = <0x1 0x0>;
			compatible = "xlnx,axi-ethernet-1.00.a";
			device_type = "network";
			interrupt-names = "interrupt";
			interrupt-parent = <0xf>;
			interrupts = <0x6 0x2>;
			local-mac-address = [00 0a 35 00 1e 52];
			phandle = <0xe>;
			phy-handle = <0x11>;
			phy-mode = "sgmii";
			reg = <0x81000000 0x40000>;
			status = "okay";
			xlnx = <0x0>;
			xlnx,axiliteclkrate = <0x0>;
			xlnx,axisclkrate = <0x0>;
			xlnx,clockselection = <0x0>;
			xlnx,enableasyncsgmii = <0x0>;
			xlnx,gt-type = <0x0>;
			xlnx,gtinex = <0x0>;
			xlnx,gtlocation = <0x0>;
			xlnx,gtrefclksrc=<0x0>;
			xlnx,include-dre;
			xlnx,instantiatebitslice0 = <0x0>;
			xlnx,phy-type = <0x4>;
			xlnx,phyaddr = <0xb>;
			xlnx,rable = <0x0>;
			xlnx,rxcsum = <0x2>;
			xlnx,rxlane0-placement = <0x0>;
			xlnx,rxlane1-placement = <0x0>;
			xlnx,rxmem = <0x8000>;
			xlnx,rxnibblebitslice0used = <0x0>;
			xlnx,tx-in-upper-nibble = <0x1>;
			xlnx,txcsum = <0x2>;
			xlnx,txlane0-placement = <0x0>;
			xlnx,txlane1-placement = <0x0>;

			axi_ethernet_11_mdio: mdio {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x3b>;

				phy11: phy@11 {
					device_type = "ethernet-phy";
					phandle = <0x11>;
					reg = <0xb>;
				};
			};
		};

 

 

And my DTSI (inspired from XAPP1082):

 

 

&axi_ethernet_11 {
	status="okay";
	local-mac-address = [00 0a 35 00 1e 52];
};

 

 

 

Okay, so there are 2 PHY on the MDIO bus then: the AXI Ethernet PHY, and the Marvell PHY.

The Marvell PHY is set to address 1 (CONFIG pin tied to LED[0]). The AXI Ethernet PHY is at address 11 (hence why I see its 0x5d03 identifier).

Now I can see the Marvell PHY if I look at address 1:

 

 

[root@q7-revb-8038 ~]$ mii-tool -v -v eth1 -p 1
Using SIOCGMIIPHY=0x8947
using the specified MII index 1.
eth1: negotiated 100baseTx-FD, link ok
  registers for MII PHY 1:
    1140 796d 0141 0dd1 01e1 cde1 000d 2001
    6001 0300 4000 0000 0000 0003 0000 3000
    3060 6c08 0000 0000 0020 0000 0000 0000
    0000 0000 0040 0000 0000 0000 0000 0000
  product info: vendor 00:50:43, model 29 rev 1
  basic mode:   autonegotiation enabled
  basic status: autonegotiation complete, link ok
  capabilities: 1000baseT-HD 1000baseT-FD 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD
  advertising:  100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD
  link partner: 1000baseT-HD 1000baseT-FD 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD flow-control

 

 

It looks like the Marvell PHY is fine and the MDIO bus too, as I can see the proper ID (0x5043) and even what the link partner (connected laptop) advertises, correct?

Do I need to only have the Marvell PHY declared in the DTS file? If so, what is the proper syntax in the DTSI file to do so?

0 Kudos
csommer
Observer
Observer
462 Views
Registered: ‎02-03-2021

Hi @nanz ,

Is this the proper DTS file syntax?

		axi_dma_eth11: dma@80400000 {
			#dma-cells = <0x1>;
			axistream-connected = <0xd>;
			axistream-control-connected = <0xd>;
			clock-names = "s_axi_lite_aclk";
			clocks = <0x1 0xf>;
			compatible = "xlnx,eth-dma";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <0xe>;
			interrupts = <0x5 0x2 0x4 0x2>;
			phandle = <0xf>;
			reg = <0x80400000 0x10000>;
			xlnx,include-dre;
		};

		axi_ethernet_11: ethernet@81000000 {
			axistream-connected = <0xf>;
			axistream-control-connected = <0xf>;
			clock-frequency = <0x5f5e100>;
			clock-names = "ref_clk";
			clocks = <0x1 0x0>;
			compatible = "xlnx,axi-ethernet-1.00.a";
			device_type = "network";
			interrupt-names = "interrupt";
			interrupt-parent = <0xe>;
			interrupts = <0x6 0x2>;
			local-mac-address = [00 0a 35 00 1e 52];
			phandle = <0xd>;
			phy-handle = <0x10>;
			phy-mode = "sgmii";
			reg = <0x81000000 0x40000>;
			status = "okay";
			xlnx = <0x0>;
			xlnx,axiliteclkrate = <0x0>;
			xlnx,axisclkrate = <0x0>;
			xlnx,clockselection = <0x0>;
			xlnx,enableasyncsgmii = <0x0>;
			xlnx,gt-type = <0x0>;
			xlnx,gtinex = <0x0>;
			xlnx,gtlocation = <0x0>;
			xlnx,gtrefclksrc=<0x0>;
			xlnx,include-dre;
			xlnx,instantiatebitslice0 = <0x0>;
			xlnx,phy-type = <0x4>;
			xlnx,phyaddr = <0xb>;
			xlnx,rable = <0x0>;
			xlnx,rxcsum = <0x2>;
			xlnx,rxlane0-placement = <0x0>;
			xlnx,rxlane1-placement = <0x0>;
			xlnx,rxmem = <0x8000>;
			xlnx,rxnibblebitslice0used = <0x0>;
			xlnx,tx-in-upper-nibble = <0x1>;
			xlnx,txcsum = <0x2>;
			xlnx,txlane0-placement = <0x0>;
			xlnx,txlane1-placement = <0x0>;

			axi_ethernet_11_mdio: mdio {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x3b>;

				phy1: phy@1 {
					compatible = "marvell,88e1510";
					device_type = "ethernet-phy";
					phandle = <0x10>;
					reg = <0x1>;
				};

				phy11: phy@11 {
					device_type = "ethernet-phy";
					phandle = <0x3c>;
					reg = <0xb>;
				};
			};
		};
0 Kudos
nanz
Moderator
Moderator
417 Views
Registered: ‎08-25-2009

Hi @csommer ,

The driver does not support shared MDIO with AXI Ethernet. You can just leave the Marvel PHY in the MDIO node and then manually disabled the isolate bit of the AXI Ethernet PHY. It will work. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
0 Kudos
csommer
Observer
Observer
390 Views
Registered: ‎02-03-2021

Hi @nanz ,

Thanks for your answer. I got the DTS updated like so:

		axi_ethernet_11: ethernet@81000000 {
			axistream-connected = <0xf>;
			axistream-control-connected = <0xf>;
			clock-frequency = <0x5f5e100>;
			clock-names = "ref_clk";
			clocks = <0x1 0x0>;
			compatible = "xlnx,axi-ethernet-1.00.a";
			device_type = "network";
			interrupt-names = "interrupt";
			interrupt-parent = <0xe>;
			interrupts = <0x6 0x2>;
			local-mac-address = [00 0a 35 00 1e 52];
			phandle = <0xd>;
			phy-handle = <0x10>;
			phy-mode = "sgmii";
			reg = <0x81000000 0x40000>;
			status = "okay";
			xlnx = <0x0>;
			xlnx,axiliteclkrate = <0x0>;
			xlnx,axisclkrate = <0x0>;
			xlnx,clockselection = <0x0>;
			xlnx,enableasyncsgmii = <0x0>;
			xlnx,gt-type = <0x0>;
			xlnx,gtinex = <0x0>;
			xlnx,gtlocation = <0x0>;
			xlnx,gtrefclksrc=<0x0>;
			xlnx,include-dre;
			xlnx,instantiatebitslice0 = <0x0>;
			xlnx,phy-type = <0x4>;
			xlnx,phyaddr = <0xb>;
			xlnx,rable = <0x0>;
			xlnx,rxcsum = <0x2>;
			xlnx,rxlane0-placement = <0x0>;
			xlnx,rxlane1-placement = <0x0>;
			xlnx,rxmem = <0x8000>;
			xlnx,rxnibblebitslice0used = <0x0>;
			xlnx,tx-in-upper-nibble = <0x1>;
			xlnx,txcsum = <0x2>;
			xlnx,txlane0-placement = <0x0>;
			xlnx,txlane1-placement = <0x0>;

			mdio {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x3b>;

				phy1: phy@1 {
					compatible = "marvell,88e1510";
					device_type = "ethernet-phy";
					phandle = <0x10>;
					reg = <0x1>;
				};
			};
		};

 

I can still see the MDIO registers of the Marvell PHY, but not the ones of the AXI Ethernet PHY anymore. How can I manually set the isolate bit of the AXI Ethernet PHY to zero?

0 Kudos
nanz
Moderator
Moderator
376 Views
Registered: ‎08-25-2009

Hi @csommer ,

Are you able to access the registers of SGMII PHY? If so, you can use devmem to manually set it.


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
csommer
Observer
Observer
362 Views
Registered: ‎02-03-2021

Hi @nanz ,

In my first posts, I could access the registers of the AXI Ethernet PHY, confirmed by reading 0x5d03 (Xilinx PHY id) at MII index 11 (MDIO PHY address set in IP).
But now I am only able to read the Marvell PHY registers, confirmed by reading 0x5043 (Marvell PHY id) at MII index 1.
mii-tool indicates that there are no mii transceiver present at 11. Is that an issue?

Can the internal AXI Ethernet PHY be configured through the registers described in xilinx_axienet.h?
I ran an ethtool register dump and mapped the data together, but the header doesn't mention the isolate bit of the internal PHY.

0 Kudos
nanz
Moderator
Moderator
338 Views
Registered: ‎08-25-2009

Hi @csommer ,

Do you by any chance have ethtool registers dumps for both previous MII addr 11 and the updated project? If so, can you please share them?


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
0 Kudos
csommer
Observer
Observer
324 Views
Registered: ‎02-03-2021

Hi @nanz ,

This is the ethtool registers dump of the updated project:

 

[root@q7-revb-8038 ~]$ ethtool -d eth1
Offset          Values
------          ------

0x0000:         00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00
0x0010:         00 00 00 00 18 00 00 00 00 00 00 00 00 00 00 00
0x0020:         00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0030:         00 08 00 00 ff ff ff ff ff ff 00 18 00 00 00 18
0x0040:         00 00 00 60 00 00 00 80 d0 07 00 00 53 00 00 00
0x0050:         80 80 0a 01 00 00 00 00 00 00 01 00 01 00 00 00
0x0060:         00 00 00 00 00 00 00 00 00 00 00 00 00 1b c5 03
0x0070:         c1 a1 00 00 03 00 00 00 01 80 c2 00 00 0e 00 00

 

 

The only other register dump I found from April 14 was when I was playing with the AXI Ethernet PHY addresses. You can see that the MII addr is not 11 but 10.

 

[root@q7-revb-6016 ~]$ ethtool -d eth1
Offset          Values
------          ------

0x0000:         00 00 00 00 00 00 00 00 00 00 00 00 c0 01 00 00
0x0010:         00 00 00 00 18 00 00 00 00 00 00 00 00 00 00 00
0x0020:         00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0030:         10 08 00 00 ff ff ff ff ff ff 00 18 00 00 00 18
0x0040:         00 00 00 60 00 00 00 00 d0 07 00 00 53 00 00 00
0x0050:         80 80 05 0a 40 13 00 00 01 00 01 00 01 00 00 00
0x0060:         00 00 00 00 00 00 00 00 00 00 00 00 00 0a 35 00
0x0070:         22 01 00 00 03 00 00 00 01 80 c2 00 00 0e 00 00

I will flash the April 14 post #1 version later today and update this reply with the proper MII addr 11 ethtool reg dump.

 

 

 

0 Kudos
csommer
Observer
Observer
252 Views
Registered: ‎02-03-2021

The 125 MHz differential clock was badly soldered (not the same board as April 14 post), so the PCS/PMA IP could not function properly, my bad...
After fixing that, I can see the internal AXI Ethernet PHY at address 11 on the latest project.


MII 11 MDIO registers:

 

 

[root@q7-revb-8038 ~]$ mii-tool eth0 -v -v -p 11
Using SIOCGMIIPHY=0x8947
using the specified MII index 11.
eth0: no link
  registers for MII PHY 11:
    1140 01c8 0174 0c00 0001 0001 0004 0000
    0000 0000 0000 0000 0000 0000 0000 8000
    0001 0001 0003 0000 0000 0000 0000 0000
    0000 0000 0000 0000 0000 0000 0000 0000
  product info: vendor 00:5d:03, model 0 rev 0
  basic mode:   autonegotiation enabled
  basic status: no link
  capabilities:
  advertising:

 

 

 

MII 1 MDIO registers:

 

 

[root@q7-revb-8038 ~]$ mii-tool eth0 -v -v -p 1
Using SIOCGMIIPHY=0x8947
using the specified MII index 1.
eth0: negotiated 1000baseT-FD flow-control, link ok
  registers for MII PHY 1:
    1000 796d 0141 0dd1 01e1 cde1 000d 2001
    4006 0300 3800 0000 0000 0003 0000 3000
    3060 ac08 0000 0000 0020 0000 0000 0000
    0000 0000 0040 0000 0000 0000 0000 0000
  product info: vendor 00:50:43, model 29 rev 1
  basic mode:   autonegotiation enabled
  basic status: autonegotiation complete, link ok
  capabilities: 1000baseT-HD 1000baseT-FD 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD
  advertising:  1000baseT-FD 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD
  link partner: 1000baseT-HD 1000baseT-FD 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD flow-control

 

 

 

In both 1 and 11, register 0 bit 10 is at 0 (= normal operation).

 

Ethtool registers dump:

 

 

[root@q7-revb-8038 ~]$ ethtool -d eth0
Offset          Values
------          ------
0x0000:         00 00 00 00 00 00 00 00 00 00 00 00 e0 01 00 00
0x0010:         00 00 00 00 18 00 00 00 00 00 00 00 00 00 00 00
0x0020:         00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0030:         50 08 00 00 ff ff ff ff ff ff 00 18 00 00 00 18
0x0040:         00 00 00 60 00 00 00 80 d0 07 00 00 53 00 00 00
0x0050:         80 80 0a 01 40 11 00 00 00 38 01 00 01 00 00 00
0x0060:         00 00 00 00 00 00 00 00 00 00 00 00 00 1b c5 03
0x0070:         c1 a1 00 00 03 00 00 00 01 80 c2 00 00 0e 00 00

 

 

 

Pinging does not leave the board (activity LEDs only blink when pinging from laptop):

 

 

[root@q7-revb-8038 ~]$ ifconfig eth0
eth0      Link encap:Ethernet  HWaddr 00:1b:c5:03:c1:a1
          inet addr:169.254.129.3  Bcast:169.254.255.255  Mask:255.255.0.0
          UP BROADCAST RUNNING  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:40 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:9548 (9.3 KiB)

 

 


According to the following diagram (PG047 page 145), I need to read SGMII reg 4 of the Marvell PHY in the AXI Ethernet PHY reg 5, and vice-versa.

csommer_0-1619826838304.png

By reading page 1, reg 4 and 5 of the Marvell PHY, I get respectively 0x9901 (link is up, FD, 1Gpbs) and 0x0000 (expecting 0x0001 from AXI Ethernet PHY, datasheet confirms that too).
And reg 5 of AXI Ethernet PHY is not at 0x9901, but the default value of 0x0001.
So there must be something wrong with the SGMII link.

0 Kudos
csommer
Observer
Observer
200 Views
Registered: ‎02-03-2021

I found a potential issue after reading Layout and Placement of PG047.
On our XC7Z020CLG484-2, I set the SGMII lines as follows:

sgmii_txp - H19 - byte group 3
sgmii_txn - H20 - byte group 3
sgmii_rxp - G17 - byte group 0
sgmii_rxn - F17 - byte group 0

Could that be the problem?

0 Kudos
csommer
Observer
Observer
88 Views
Registered: ‎02-03-2021

PG047 says "All the transmitter and receiver lanes should be within the same BYTE_GROUP".
Is that a requirement or a recommendation? Can it work if the lanes are not in the same BYTE_GROUP?

Also, according to this post, since LVDS_25 and CML (at 1.8V) are not compatible, I need to have AC coupling between the 88E1512 and the Zynq SGMII TX and RX pairs, as well as DC biasing on the RX pairs of the FPGA.
https://forums.xilinx.com/t5/Ethernet/ZYNQ-7000-SGMII-on-LVDS-pins/td-p/955620
As anyone done this and did it work?

0 Kudos