cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
4,116 Views
Registered: ‎11-25-2012

Two Tri mode MAC core in one project can not work.

Hi all,

 

      We need two 1G Ethernet ports on Kintex-7 FPGA to communicate with PC. First, we used the example design to implement a project with one Tri-mode MAC. It can work well. And then, we tried to intantiate two instance in a project. We found a strange phenomenon. The rx_reset signal stay on 1 and the two ports can not work.  This signal is driven by the MAC core module, so I'm afraid that we can not find the reason. How can we solve this problem? Need your help. Thanks a lot.

 

We are using ISE 14.7 and the version of Tri-mode MAC is 5.5.

0 Kudos
6 Replies
Highlighted
Visitor
Visitor
4,110 Views
Registered: ‎11-25-2012

And I opened the FPGA editor to find the rx_reset signal, but I can not find it at all. However, in the one MAC version, I can find this signal in PAR FPGA editor.  I am so puzzled.

0 Kudos
Highlighted
Scholar
Scholar
4,040 Views
Registered: ‎08-07-2014

The rx_reset signal stay on 1 and the two ports can not work. 

 

Have you checked the reset generation block? It is the one which generates the sync resets.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer solved your problem.
-------------------------------------------------------------------------------------------------------
0 Kudos
Visitor
Visitor
4,026 Views
Registered: ‎11-25-2012

Yes,we have checked it.  rx_axi_rstn and glbl_rstn are low and bus2ip_reset is 1, while the signal int_rx_rst cannot be checked.

reset.png

 

0 Kudos
Highlighted
Visitor
Visitor
4,025 Views
Registered: ‎11-25-2012

I guess that this problem is related the configuration logic, but I do not know how to solve this problem.

0 Kudos
Highlighted
Scholar
Scholar
4,008 Views
Registered: ‎08-07-2014

Then I would ask whether you are using a single config_logic module for both cores or separate config_logic for both cores.

In my multi-TEMAC core design, I use a common resets block but separate config_logic blocks.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer solved your problem.
-------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
3,963 Views
Registered: ‎02-06-2013

Hi,

rx_axi_rstn and glbl_rstn are active low signals and if you are driving them to low then the core will be in reset.
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos