10-10-2016 10:54 PM
We need two 1G Ethernet ports on Kintex-7 FPGA to communicate with PC. First, we used the example design to implement a project with one Tri-mode MAC. It can work well. And then, we tried to intantiate two instance in a project. We found a strange phenomenon. The rx_reset signal stay on 1 and the two ports can not work. This signal is driven by the MAC core module, so I'm afraid that we can not find the reason. How can we solve this problem? Need your help. Thanks a lot.
We are using ISE 14.7 and the version of Tri-mode MAC is 5.5.
10-10-2016 11:00 PM
And I opened the FPGA editor to find the rx_reset signal, but I can not find it at all. However, in the one MAC version, I can find this signal in PAR FPGA editor. I am so puzzled.
10-13-2016 01:19 AM
The rx_reset signal stay on 1 and the two ports can not work.
Have you checked the reset generation block? It is the one which generates the sync resets.
10-13-2016 07:58 AM
Yes,we have checked it. rx_axi_rstn and glbl_rstn are low and bus2ip_reset is 1, while the signal int_rx_rst cannot be checked.
10-13-2016 08:02 AM
I guess that this problem is related the configuration logic, but I do not know how to solve this problem.
10-14-2016 02:22 AM
Then I would ask whether you are using a single config_logic module for both cores or separate config_logic for both cores.
In my multi-TEMAC core design, I use a common resets block but separate config_logic blocks.
10-16-2016 09:59 PM