03-17-2019 07:09 AM
I'm looking for 100G initialization example source code. I'm wondering if someone can point me to the source location.
03-17-2019 10:59 AM
hi @syuriks ,
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PCS) core for high performance applications. The core is designed to the IEEE 802.3-2012 specification in the latest UltraScale™.
The Xilinx 100 Gbps Ethernet MAC and PCS core provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode.
The Xilinx 100 Gbps Ethernet MAC and PCS core also enables optional fee-based features for the IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) and 100GE Auto-Negotiation/Link Training (AN/LT) IP to enable solutions such as KR4, CR4, SR4, CWDM4, PSM4, or ER4f for high performance applications.
Please see the pg165.
let us know your inputs
03-18-2019 01:14 AM
I've read this product guide. I'm looking for some code sample implementing device initialization.
03-20-2019 12:39 PM
hi @syuriks ,
i am sorry i did not get you , if i am wrong please correct me .
generally you can see the device ulilization once you confugure the IP core
03-20-2019 01:16 PM