11-20-2019 01:03 AM
I am simulating the example design of the ultrascale+ 100G IP, using the vivado 2019.1.3 and modelsim tools to simulate the IP, by followed the pg203, i did define SIM_SPEED_UP in the testbench, but for now, i had done the simulation for three days, the signal of rx_done_led in the pkt_gen_mon module is still deasserted, which caused the simulation is still unfinished, but all the stat signals seemed to be normal, the stat_rx_aligned and the stat_rx_status signals were hign level now, and the transmit signals had sent the patterns, only the reveive path got nothing, is this a normal phenomenon, or just i wait for finished?
The modelsim scripts show below:
# INFO : SYS_RESET RELEASED TO CMAC IP
# INFO : WAITING FOR THE GT LOCK..........
# INFO : GT LOCKED
# Core_Version = 2.6
# INFO : WAITING FOR CMAC RX_ALIGNED..........
# INFO : RS-FEC IS ENABLED
# INFO : RX-ALIGNED
# INFO : Packet Generator and Monitor (SANITY Testing) STARTED
# Number of data packets to be transmitted = 1000, each of packet size = 522Bytes, Total bytes: PKT_NUM * (PKT_SIZE + 4[CRC]) = 526000Bytes
# INFO : ALL PACKETS SENT, NO ERRORS
The pics of modelsim scripts and wave list below:
11-28-2019 11:18 PM
Do you mean Packets are sent on TX while RX doesn't receive any?
Is this IP core example design? Have you tried Vivado Simulator?
11-28-2019 11:25 PM
Yes，it is the example design with the definition of SIM_SPEED_UP, and both Modelsim and Vivado Simulator had been tried.
Packets are sent on TX corectly, but RX receiver none.
11-28-2019 11:36 PM
03-05-2020 10:47 AM
Hi @guozhenp ,
I'm seeing the same issue with CMAC core revision 3.0 and Vivado 2019.2. Example design simulation doesn't progress beyond "WAITING FOR CMAC RX_ALIGNED". It run overnight and simulated 5.3ms. I tried multiple config options, including disabling RS-FEC. Also tried adding "xvlog -d SIM_SPEED_UP" option and making sure it applied.
Attached is my CMAC configuration.