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Contributor
Contributor
264 Views
Registered: ‎05-04-2017

Ultrascale+ 100G cmac simulation time too long

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I am simulating the example design of the ultrascale+ 100G IP, using the vivado 2019.1.3 and modelsim tools to simulate the IP, by followed the pg203, i did define SIM_SPEED_UP in the testbench, but for now, i had done the simulation for three days, the signal of rx_done_led in the pkt_gen_mon module is still deasserted, which caused the simulation is still unfinished, but all the stat signals seemed to be normal, the stat_rx_aligned and the stat_rx_status signals were hign level now, and the transmit signals had sent the patterns, only the reveive path got nothing, is this a normal phenomenon, or just i wait for finished?

The modelsim scripts show below:

# INFO : SYS_RESET RELEASED TO CMAC IP
# INFO : WAITING FOR THE GT LOCK..........
# INFO : GT LOCKED
# Core_Version = 2.6
# INFO : WAITING FOR CMAC RX_ALIGNED..........
# INFO : RS-FEC IS ENABLED
# INFO : RX-ALIGNED
# INFO : Packet Generator and Monitor (SANITY Testing) STARTED
# Number of data packets to be transmitted = 1000, each of packet size = 522Bytes, Total bytes: PKT_NUM * (PKT_SIZE + 4[CRC]) = 526000Bytes
# INFO : ALL PACKETS SENT, NO ERRORS

The pics of modelsim scripts and wave list below:

modelsim_scripts.png
modelsim_wave.png
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1 Solution

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Contributor
Contributor
89 Views
Registered: ‎05-04-2017

回复: Ultrascale+ 100G cmac simulation time too long

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Vivado 2019.2 fixed this issue, both modelsim and Vivado worked well

View solution in original post

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6 Replies
Contributor
Contributor
201 Views
Registered: ‎05-04-2017

回复: Ultrascale+ 100G cmac simulation time too long

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It is four days now, i am now considering that there are likely to have some bugs in the IP intergrated in Vivado 2019.1.3
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Xilinx Employee
Xilinx Employee
159 Views
Registered: ‎05-01-2013

回复: Ultrascale+ 100G cmac simulation time too long

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Do you mean Packets are sent on TX while RX doesn't receive any?

Is this IP core example design? Have you tried Vivado Simulator?

 

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Contributor
Contributor
155 Views
Registered: ‎05-04-2017

回复: Ultrascale+ 100G cmac simulation time too long

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Yes,it is the example design with the definition of SIM_SPEED_UP, and both Modelsim and Vivado Simulator had been tried.

Packets are sent on TX corectly, but RX receiver none.

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Xilinx Employee
Xilinx Employee
152 Views
Registered: ‎05-01-2013

回复: Ultrascale+ 100G cmac simulation time too long

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Please try 2019.2

Please provide the IP core configurations

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Contributor
Contributor
141 Views
Registered: ‎05-04-2017

回复: Ultrascale+ 100G cmac simulation time too long

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I had just updated the Vivado to 2019.2, but since the core version(v3.0) is still same with 2019.1, i don't think there will any changes.
The IP core configurations is CAUI4, 161.1328125Mhz, AXIS interface, RS-FEC enabled and AN/LT disabled.
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Contributor
Contributor
90 Views
Registered: ‎05-04-2017

回复: Ultrascale+ 100G cmac simulation time too long

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Vivado 2019.2 fixed this issue, both modelsim and Vivado worked well

View solution in original post

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