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Visitor
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Registered: ‎05-31-2018

Ultrascale+ 2 100G CMACs on the same reference clock

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I'm currently working with Alpha Data 9H3 board with XCVU33P-2E FPGA. The board has QSFP-DD cage, which allows to input 2x100G with proper fiber optic cabling. However the board offers single GT reference clock and cmac_usplus needs differential clock, so one cannot simply connected gt_ref_clock_out of one cmac to gt_ref_clock of the other one. Is it somehow possible to drive both CMACs from the same clock or one needs two seperate suitable clocks?

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Moderator
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Registered: ‎04-01-2018

Re: Ultrascale+ 2 100G CMACs on the same reference clock

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Hi @fleonarski 

I beleive you can use Include GT Subcore in Example Design to chose the reference clock when GT is out side of the core but there are two concerns where you may not be able to share the clock:

 

1) If the CMAC X0Y0 has GT's selected for Left Coloumn and CMAC X0Y1 has GT's selected for Right Coloumn and viceversa

eg: CMAC X0Y0 - selected with GT (X0Y2) X0Y8-X0Y11 (MGTREFCLK0) and CMAC X0Y1 - selected with GT (X1Y1)  X1Y4-X1Y7 not a possible case

     CMAC X0Y0 - selected with GT (X0Y2)  X0Y8-X0Y11 (MGTREFCLK0) and CMAC X0Y1 selected with GT (X0Y3) X0Y12-X0Y15 can take clock as MGTREFCLK0 of Quad X0Y2 (-1)

 

2) If the CMAC X0Y0 has the Quad selected in the TOP and CMAC X0Y1 has Quad Selected in the BOTTOM (this applies for both Left and Right Coloumn)

eg: CMAC X0Y0 (MGTREFCLK0)-  with Quad X0Y0 and CMAC X0Y3 (it can only take Clock from Quad X0Y2)

 

Please use the FPGA Transceiver Wizard in Vivado to further to check with the possible clock options for your device (Physcial Resources TAB)

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Moderator
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Registered: ‎04-01-2018

Re: Ultrascale+ 2 100G CMACs on the same reference clock

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Hi @fleonarski 

I beleive you can use Include GT Subcore in Example Design to chose the reference clock when GT is out side of the core but there are two concerns where you may not be able to share the clock:

 

1) If the CMAC X0Y0 has GT's selected for Left Coloumn and CMAC X0Y1 has GT's selected for Right Coloumn and viceversa

eg: CMAC X0Y0 - selected with GT (X0Y2) X0Y8-X0Y11 (MGTREFCLK0) and CMAC X0Y1 - selected with GT (X1Y1)  X1Y4-X1Y7 not a possible case

     CMAC X0Y0 - selected with GT (X0Y2)  X0Y8-X0Y11 (MGTREFCLK0) and CMAC X0Y1 selected with GT (X0Y3) X0Y12-X0Y15 can take clock as MGTREFCLK0 of Quad X0Y2 (-1)

 

2) If the CMAC X0Y0 has the Quad selected in the TOP and CMAC X0Y1 has Quad Selected in the BOTTOM (this applies for both Left and Right Coloumn)

eg: CMAC X0Y0 (MGTREFCLK0)-  with Quad X0Y0 and CMAC X0Y3 (it can only take Clock from Quad X0Y2)

 

Please use the FPGA Transceiver Wizard in Vivado to further to check with the possible clock options for your device (Physcial Resources TAB)

-----------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------------

View solution in original post