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Matteo_Zini
Observer
Observer
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Registered: ‎07-29-2020

Ultrascale+ - Ethernet burst size

Good morning,


I am a student currently invenstigating the I/O components of the ultrascale+ SoC on a zcu-102 board.
Studying the behaviour of the ethernet DMA, I measured the generated traffic with the Axi performance monitors (APM), while testing every possible configuration of burst size with the DMA configuration register.

However, from the measurements of both the number of bytes and the number of transactions by the APM, I noticed that the rate of bytes per transaction for read operations is double with respect to the expected value. 

For example, if I set the burst size to 1, I would expect to see a maximum value of 8 bytes per transaction, given that the manual states that the word size for the Ethernet DMA is 64 bits.  However, I constantly see 16 bytes per transaction. This behaviour persists even changing the burst size value to 4, 8 or 16, and I always see a value that is two times the expected one.

since I cannot find a reason for this behavior, I wanted to ask wheter someone knows whts this is due to.

 

Thank you.

Matteo Zini

 

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4 Replies
nanz
Moderator
Moderator
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Registered: ‎08-25-2009

Hi @Matteo_Zini ,

What is the Ethernet DMA you meant? Which IP do you use? Do you have Ethernet IP in your design that is connected to AXI DMA? There is no specific IP called Ethernet DMA. Please specify. 


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Matteo_Zini
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Registered: ‎07-29-2020

Hi and thanks for the reply.

I'm referring to the DMA controller described at page 1040 of the Ultrascale+ reference manual https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Matteo Zini

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nanz
Moderator
Moderator
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Registered: ‎08-25-2009

Hi @Matteo_Zini ,

This DMA controller is a dedicated controller for GEM inside PS. I wonder how did you attach Axi performance monitors (APM) to this DMA as it's not accessible to outside world.

If you have a block diagram to share, that will be great. Thank you!


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Matteo_Zini
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Observer
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Registered: ‎07-29-2020

Hi @nanz ,

I utilised the APMs that are already available on the Ultrascale+; in particular the one between the LPD main switch and the CCI. Given that the other traffic passing from that point, while performing the tests, is negligible, the measurements showed the behaviour mentioned above.

This is the schema of the SoC: the red arrow is the path used by the DMA to access memory, and the APM is in the yellow ellipse.

Matteo_Zini_0-1612370613841.png

Thank you.

Matteo Zini

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