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Contributor
Contributor
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Registered: ‎08-28-2014

Ultrascale MAC throttles transfer

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I am implementing a design in a UltraZed-EG from Avnet with a XZCU3 device.  The design is required to transmit data from external ADCs to an external processor utilizing the ethernet port via the FIFO interface from the PL.  When I transmit the data the MAC is throttling the transfer which prevents one continuous burst.  After the transfer begins the tx_r_rd is asserted for 4 clocks and de-asserted for 4 clocks until the burst end of packet.  The largest packet in 512 bytes.  The diagram ee1 illustrates the beginning of the transfer and ee2 is a continuation of the transfer.

Is there are setting in a MAC register that would cause this behavior?

ee1.JPG
ee2.JPG
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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @aldopowell ,

Are you runnning at 10/100Mbps?

At 1G, it may request data more often than 4 cycles only if there is less than 32 bits to transfer, which can only occur at EOP (via the tx_r_mod signaling), but it may be set >4cycles apart as a result of the MAC inserting preamble, the SFD, CRC or IPG. 

 

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @aldopowell ,

I presume you are using PS GEM on ZU+ devices with external FIFO interface enabled.

If you look at network_configuration register, bit [22:21] data_bus_width, you will see this is set to "00", ie, 32-bit data bus width when External FIFO Interface is enabled. And the external FIFO Interface is actually a 8 bit interface. So on average the existing TX FIFO interface will request data via the tx_r_rd output every 4 cycles for gigabit modes (less for 10/100 modes). 

 

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Contributor
Contributor
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Registered: ‎08-28-2014

Since you state that tx_r_rd would be throttled less for 10/100, it would match what I am seeing in AR# 69490.

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Moderator
Moderator
430 Views
Registered: ‎08-25-2009

Hi @aldopowell ,

Are you runnning at 10/100Mbps?

At 1G, it may request data more often than 4 cycles only if there is less than 32 bits to transfer, which can only occur at EOP (via the tx_r_mod signaling), but it may be set >4cycles apart as a result of the MAC inserting preamble, the SFD, CRC or IPG. 

 

"Don't forget to reply, kudo and accept as solution."

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Contributor
Contributor
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Registered: ‎08-28-2014

I am operating at 1G.

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