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mtnli89
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Registered: ‎11-29-2020

Using 10G ethernet Subsystem IP Core for kintex 7 FPGA

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Hi every one,

I want to run sfp+ on my board which has xc7k410tffg676-2 FPGA, but I have a problem. In Vivado for this kind of FPGA there isn't any "gt selection and configuration tab" to choose the location of gtx as like as the one for ultrascale FPGAs. So how can I choose the gtx location. Adding rxp and refclk as like as below is anough?

set_property PACKAGE_PIN N4 [get_ports rxp]
set_property PACKAGE_PIN H6 [get_ports refclk_p]

Thanks 

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guozhenp
Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

Normally, we add GT reference clock pin location and GT location constraints.

Maybe you can generate GT example to check its constraints.

Or read GT UG directly.

View solution in original post

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guozhenp
Xilinx Employee
Xilinx Employee
273 Views
Registered: ‎05-01-2013

Normally, we add GT reference clock pin location and GT location constraints.

Maybe you can generate GT example to check its constraints.

Or read GT UG directly.

View solution in original post