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Participant peter.lieber
Participant
2,181 Views
Registered: ‎08-10-2010

V6 GTX wizard example (rx_sync)

We are designing a front end that needs to simply deserialize the stream.  I have simulated, disabling all the rx_buffers, decoding, and channel bonding, etc. It all works great (after fixing a tiny bug in the generated code). 

 

Now, I need to dumb it down even more and want to understand everything I have generated. I took out the frame checker and the aligner with no issues.  In the GTX user guide, it says I need to include the rx_sync module for each tranceiver that I bypass the buffer.  I am willing to do that, but I am not sure what is happening in there.

 

The only inputs to the rx_sync module are a reset and clock.  This clock is the usr_clk2, which is tied to pllrec_clk.  The reset signal, after removing the aligner module, is just high until the GTX reset done signal is asserted.   Then, the rx_sync module asserts the various phase align signals going to the GTX.  My questions are:

 

1. Why do the phase alignment signals need to be asserted in this order and with 32 cycles in betwen?

2. Why not assert these signals once the reset is done.

3. If the pll loses lock, it seems that you would want to realign the phase, but the GTX0_RXPLLLKDET_OUT signal does not seem to trigger any of this in the example design.

 

I am new at high speed serial, so thank you for helping my ignorance.  Attached is my dumbed down top level example file.

Peter

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