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Mentor
Mentor
5,304 Views
Registered: ‎06-09-2011

V6EMAC ready signal doesn't work properly

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Hi all,

I am developing VHDL code for ML605 and I have created an Ethernet core without AXI-Lite management unit. I have implemented all necessary signals - specifically 125MHz clock to have 1Gbps GMII interface.Below is the instantiation module:

 

MyETH_INST : MyETH
	port map (
	glbl_rstn 					=> sETH_RST,
	rx_axi_rstn 				=> sETH_RST,
	tx_axi_rstn 				=> sETH_RST,
	gtx_clk 					=> sSYSCLK,
-----		RX 	AXI4-Stream Interface	-----------------------
	rx_axi_clk 					=> sSYSCLK,
	-- rx_reset_out 				=> rx_reset_out,
	
	-- rx_axis_mac_tdata 			=> rx_axis_mac_tdata,
	-- rx_axis_mac_tvalid 			=> rx_axis_mac_tvalid,
	-- rx_axis_mac_tlast 			=> rx_axis_mac_tlast,
	-- rx_axis_mac_tuser 			=> rx_axis_mac_tuser,
	
	-- rx_statistics_vector 		=> rx_statistics_vector,
	-- rx_statistics_valid 		=> rx_statistics_valid,
---------------------------------------------------------------
-----		TX 	AXI4-Stream Interface	-----------------------
	tx_axi_clk 					=> sSYSCLK,
	-- tx_reset_out 				=> tx_reset_out,
	
	tx_axis_mac_tdata 			=> sTX_MAC_DAT,
	tx_axis_mac_tvalid 			=> sTX_MAC_VAL,
	tx_axis_mac_tlast 			=> sTX_MAC_LST,
	tx_axis_mac_tuser 			=> '0',
	tx_axis_mac_tready 			=> sMAC_Ready,
	
	-- tx_retransmit 				=> tx_retransmit,
	tx_collision 				=> tx_collision,
	tx_ifg_delay 				=> (others => '0'),
	tx_statistics_vector		=> tx_statistics_vector,
	tx_statistics_valid 		=> tx_statistics_valid,
---------------------------------------------------------------
	pause_req 					=> '0',
	pause_val 					=> (others => '0'),
	speed_is_10_100 			=> oLowSpeed,
--			GMII Interface					--
	gmii_txd 					=> oGMII_TXD,
	gmii_tx_en 					=> oGMII_TX_EN,
	gmii_tx_er 					=> oGMII_TX_ERR,
	gmii_rxd 					=> iGMII_RXD,
	gmii_rx_dv 					=> iGMII_RX_DV,
	gmii_rx_er 					=> iGMII_RX_ERR
);

Whenever I try to do behavioral simulation, I see that tx_axis_mac_tready signal falls as soon as I write the first byte of DA in the tx_axis_mac_tdata bus. I have monitored all signals which I thought may show the fault state of the core. however, nothing has happened to the core ready signal goes low and won't be set. I don't see why? How I can check and debug the problem? Below picture shows the case:

Ready.jpg

 

I would appreciate any help.

Hossein

 

Thanks,
Hossein
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Mentor
Mentor
9,585 Views
Registered: ‎06-09-2011

Hi @yenigal and @balkris,

 

Thank you guys for your help and comments. My problem was related to incomplete signal routing to PHY Chip in ML605. As I monitored PHY pins with oscilloscope I realized that I had not routed TXC_GTXCLK. So, I used the same 125MHz clock which is feeding my TX process and inverted it by ODDR to prevent signal delays from various gmii_TXD pins to PHY. Then everything was working properly :-)

 

Thank you again for your comments.

Hossein

Thanks,
Hossein

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Here you can find reference design for ML605 board. It may help you
http://www.xilinx.com/products/boards/ml605/reference_designs_12.1_archive.htm

 

check this post as well

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Problem-with-RGMII-on-ML605/td-p/439318

Thanks and Regards
Balkrishan
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Mentor
Mentor
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Registered: ‎06-09-2011

Hi,

Thank you for your answer. The first link doesn't contain any example regarding Ethernet. The second one also discusses another issue. I do have connected 125MHz clocks to rx_axi_clk, tx_axi_clk and GTX_CLK ! If you have seen the simulation, you would see that ready pin was asserted for some clocks. However, it's de-asserted and never goes high again. This is my problem!. I think we are better concentrate on this point and see why core stops asserting ready pin?!

 

Thanks,

Hossein

Thanks,
Hossein
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Xilinx Employee
Xilinx Employee
5,239 Views
Registered: ‎02-06-2013

Hi

 

ISIM  is not a tested and supported simulator with this core.

 

Can you try one of the supported simulator modelsim or NCSIM for simulation and let us know if you are still seeing the issue.

 

Also try with the example design generated with the core.

Regards,

Satish

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Mentor
Mentor
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Registered: ‎06-09-2011

Hi @yenigal,

Thank you for your comments.My problem was only in Behavioral simulation! I changed simulation to Post-PAR so it is working finely. I also tried that example design and downloaded it to ML605. Unfortunately, it didn't work. When I try my own developed VHDL code Duplex link LED - DS35 - and Link1000 LED - DS34 - are ON but TX LED doesn't go ON!. I have used Chip Scope and routed tx_axi_tdata as well as gmii_tx data to it. I see that whenever I write to tx_axi interface all data as well as Ethernet frame preamble and trailer are being sent to PHY chip. However, I can't see any signaling on those Pull-down resistors - RP3 - between PHY device and RJ-45 transformer?!.. It is always in 2.5V state with very very little strange low amplitude signaling on it. Can I conclude that PHY is sending something out or not?!. What seems to be the problem in this case when Wireshark doesn't show any packets received? I mean I have created correct packets and I am sending them continuously. Do I need to read what comes in the MAC and analyze it and send appropriate response or not? Do I need to enable AXI interface and configure it first? If so, isn't there any workaround to be able to work with default settings?

 

Thanks,

Hossein

 

Thanks,

Hossein

 

Thanks,
Hossein
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Xilinx Employee
Xilinx Employee
5,197 Views
Registered: ‎02-06-2013

Hi

 

Check if the jumper setting are fine for GMII mode from below doc

 

http://www.xilinx.com/support/documentation/boards_and_kits/ug534.pdf

 

You can also try enabling the PHY loopback and see if you are getting the data back.

Regards,

Satish

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Highlighted
Mentor
Mentor
9,586 Views
Registered: ‎06-09-2011

Hi @yenigal and @balkris,

 

Thank you guys for your help and comments. My problem was related to incomplete signal routing to PHY Chip in ML605. As I monitored PHY pins with oscilloscope I realized that I had not routed TXC_GTXCLK. So, I used the same 125MHz clock which is feeding my TX process and inverted it by ODDR to prevent signal delays from various gmii_TXD pins to PHY. Then everything was working properly :-)

 

Thank you again for your comments.

Hossein

Thanks,
Hossein

View solution in original post

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Mentor
Mentor
5,128 Views
Registered: ‎06-09-2011

Hi @yenigal,

Although my problem has been solved I am going to clear everything clear and I wanted to inform you that when I change my simulator to ModelSim 10.4 I receive below Error Messages:

 

##### C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\secureip\TEMAC_SINGLE.vhd(41): *p&آŒhأƒ] Dh AS أ¨? آ°fAJj آ§
# ** Error: C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\un\secureip\TEMAC_SINGLE.vhd(41): Library secureip not found.
###### C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\secureip\TEMAC_SINGLE.vhd(42): ; آگ(ABآˆآƒآ‡¬
# ** E: C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\secureip\TEMAC_SINGLE.vhd(42): (vopt-1136) Unknown identifier "secureip".
#
# ** Warning: C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\secureip\TEMAC_SINGLE.vhd(907): (vopt-3473) Component instance "/Test1/uut/MyETH_INST/BU2_U0_v6_emac/TEMAC_SINGLE_INST : TEMAC_SINGLE_WRAP" is not bound

 

It seems that this core is not in the Library Secureip?! What should I do?

 

Thanks,

Hossein

 

Thanks,
Hossein
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