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478 Views
Registered: ‎06-16-2014

VCU118 - 40G QSFP

Hi,

I have generated example design for 40G from Vivado 2018.2 and did the pin assignments as per the master constraints specified in the UG1224 document. I am using 125MHZ on board clock to generate the sable reference 100MHz clock. QSFP1 port on the VCU118 is selected.

I have connected the 40G optical cable from board to PC. with that rx_aligned signal is not going high. if I use the QSFP loopback module then the example design is working fine.

I have checked on the gt_loopback value which is 000.

I am not driving any values on the below signals from FPGA.
QSFP1_LPMODE_LS
QSFP1_MODPRSL_LS
QSFP1_MODSELL_LS
QSFP1_RESETL_LS

Kindly suggest.

Regards,

Shubha

5 Replies
Observer mwniels
Observer
263 Views
Registered: ‎06-21-2018

Re: VCU118 - 40G QSFP

Bump, I have a similar question.

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Moderator
Moderator
244 Views
Registered: ‎04-01-2018

Re: VCU118 - 40G QSFP

Hi @mwniels 

Can you try applying reset to gtwiz_reset_rx_datapath to check whether that has any effect. 

This is required after powering on, resetting or reconnecting the link partner. Timeout logic can be added to monitor if alignment has not completed and issue the gtwiz_reset_rx_datapath reset. Using gtwiz_reset_rx_datapath reset for the alignment monitoring will avoid interruption on the TX side of the link. 

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Observer mwniels
Observer
233 Views
Registered: ‎06-21-2018

Re: VCU118 - 40G QSFP


@kgadde wrote:

Hi @mwniels 

Can you try applying reset to gtwiz_reset_rx_datapath to check whether that has any effect. 

This is required after powering on, resetting or reconnecting the link partner. Timeout logic can be added to monitor if alignment has not completed and issue the gtwiz_reset_rx_datapath reset. Using gtwiz_reset_rx_datapath reset for the alignment monitoring will avoid interruption on the TX side of the link. 


I haven't been specifically asserting gtwiz_reset_rx_datapath but I have but asserting pma_init which I see is connected to this reset. PMA_init hasn't been helping at the moment.

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Adventurer
Adventurer
224 Views
Registered: ‎02-06-2018

Re: VCU118 - 40G QSFP

Some QSFP module manufactureres build-in their own RS-FEC in the module. Are you using Mellanox adapters in computer side? If you do, they do have RS-FEC *always* enabled and if your module does not provide RS-FEC, try enabling it on the cmac core and try again. 

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Observer mwniels
Observer
214 Views
Registered: ‎06-21-2018

Re: VCU118 - 40G QSFP

This is where my setup is different from the original post so I hope I'm not stepping on anyone's toes.

Mine is a 40G Aurora Link over QSFP Copper cables between a Sidewinder-100 (Zynq MPSoC) and a VCU118 card. So to answer your question, no I'm not using a mellanox card for this part of the design. My cables and board modules don't have the RS-FEC pin you referred to.

If you're interested in supporting my question further, I have a forum question about my vcu-118 question here: https://forums.xilinx.com/t5/Evaluation-Boards/Aurora-64B66B-using-VCU118-s-QSFP-Ports/td-p/997217

I appreciate the help!

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