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mdlewisfb
Visitor
Visitor
1,689 Views
Registered: ‎02-26-2019

VCU128 SGMII Core

I am trying to synthesize the SGMII 1G IP Core for the VCU128 development kit, however during the "Generate Bitstream" steps I am getting DRC errors and it fails. When I open the IP Example design and try to synthesize I get the same error. The settings are LVDS, Synchronous 625MHz clock, and including shared logic. The error is:

"[DRC PDRC-198] Serial-mode-bitslice_0_connected: SERIAL Mode: The SERAL mode nibble at BITSLICE_CONTROL cell sgmii_1g_mac/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_1.Nibble_I_BitsliceCntrl must have an RX_BITSLICE or RXTX_BITSLICE connected to bitslice position 0 with attribute DATA_TYPE set to 'SERIAL'"

How do I fix this and/or what are the correct settings for this development kit? 

8 Replies
mdlewisfb
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Registered: ‎02-26-2019

Anything? I've tried various settings for the IP and always get this error.

mdlewisfb
Visitor
Visitor
1,619 Views
Registered: ‎02-26-2019

Anything on this?

Based the pin names from the provided xdc file (here) for SGMII_RX and SGMI_TX, I have the settings as:

 

TxLane0 Placement: DIFF PAIR 1
RxLane0 Placement: DIFF PAIR 2
Tx In Upper Nibble: 1

 

I'm not sure on these last two settings, but no combination seems to work:

 

RxNibbleBitslice0Used: true
InstantiateBitslice0: true

 

With these settings I still get DRC PDRC-198 like before, but also a DRC PDRC-187 error when I try to convert to Bitstream.

The new error (-187) says:

RX_BITSLICE_CONTROL_fanout_1: RX_BITSLICE cell sgmii_1g_mac/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_5[5].Gen_5_1.Gen_5_1_0.Nibble_I_RxBitslice_n has one or more invalid bus pin connections. Each bit of the bus may only connect to a single BITSLICE_CONTROL cell pin and must be in the same nibble as the bitslice control.
Pin RX_BIT_CTRL_IN[0] is connected to a BITSLICE_CONTROL in a different nibble.
Pin TX_BIT_CTRL_OUT[0] is connected to a BITSLICE_CONTROL in a different nibble.
Pin TX_BIT_CTRL_IN[0] is connected to a BITSLICE_CONTROL in a different nibble.
Pin RX_BIT_CTRL_OUT[0] is connected to a BITSLICE_CONTROL in a different nibble.

Also same error message for Gen_5[6]. 

Is this IP Core just broken for this development board?

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abansod88
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Registered: ‎05-19-2018

Hi,

Use settings below:

RxNibbleBitslice0Used: false
InstantiateBitslice0: true

This will create a dummy_port_in at the lvds core.

Connect this to a dummy top level port and LOC it to BITSLICE0 position: BL23.

Hope this helps!

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kendrick
Adventurer
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1,215 Views
Registered: ‎01-21-2012

This worked for me to get the code to build. Thanks for the help.

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paul.mnt
Observer
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1,068 Views
Registered: ‎05-10-2013

Aren't the correct settings as follows?

TxLane0 Placement: DIFF PAIR 1
RxLane0 Placement: DIFF PAIR 0
Tx In Upper Nibble: 1

 

According to ug1302 and package-pin information, pins are :

ENET_SGMII_OUT_N   BJ21 - IO_L22N_T3U_N7_DBC_AD0N_67   3U     67    HP        0
ENET_SGMII_OUT_P   BH21 - IO_L22P_T3U_N6_DBC_AD0P_67   3U     67    HP        0

According to pin naming and to the io_bank schemeL22 should correspond to byte group 3, upper nibble, differential pair 0.

If, instead, you confirm that rx lane is on differential pair 2, which of the above references does not apply to VCU128?

 

In addition, I have a question related to the PHY: will the PHY get a reset during the power cycle, or is it mandatory to control the GEM3_ENET_RESET_B?
If reset must be controlled explicitly, is there a reference design to do so on the VCU128, for which the pin is  behind the port extender TCA6416A?

 

Thank you
-- Paolo

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instrument
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Registered: ‎01-13-2021

I've spent a lot of time debugging this myself. Here's what worked:

RxNibbleBitslice0Used: false
InstantiateBitslice0: true
TX_in_upper_nibble: true
TX Lane 0: DIFF PAIR 1
RX Lane 0: DIFF PAIR 2
paul.mnt
Observer
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712 Views
Registered: ‎05-10-2013

This is the tcl to generate the IP, with parameters that are different from the default.

paul.mnt
Observer
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Registered: ‎05-10-2013

For completeness and for future visitors: the reason why the above parameters from @instrument and my tcl script work is that the VCU128 User Guide shows incorrect pin assignments on the following table:
Table 27: XCVC37P U1 to Ethernet PHY U62 Connections.

This error is still present in the latest version UG1302 (v1.1) April 21, 2021.

These are the correct XDC entries for the rows of the table that should be corrected:

# "ENET_SGMII_CLK_P" - Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67                                                                                                                               
set_property PACKAGE_PIN BH27 [get_ports ENET_SGMII_CLK_P]

# "ENET_SGMII_CLK_N" - Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67                                                                                                                               
set_property PACKAGE_PIN BJ27 [get_ports ENET_SGMII_CLK_N]

# "ENET_SGMII_OUT_P" - # Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67                                                                                                                            
set_property PACKAGE_PIN BJ22 [get_ports ENET_SGMII_OUT_P]

# "ENET_SGMII_OUT_N" - # Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67                                                                                                                            
set_property PACKAGE_PIN BK21 [get_ports ENET_SGMII_OUT_N]

# "DUMMY_NC" - Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 (required dummy input pin!)                                                                                                      
set_property PACKAGE_PIN BL23 [get_ports DUMMY_NC]

 
Also, don't forget to add that dummy unconnected input port, or you will get errors during implementation in Vivado! 

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