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Registered: ‎10-17-2009

Virtex 5 ML510 Serial RapidIO Implementation

Hello all,


I am trying to implement the Serial RapidIO IP core on a Virtex 5 ML510 FX130T board in an external and internal loopback so that I can verify it and had a few questions.  


1) Does anyone know of any documentation that describes the process of getting the board to perform in the loopback mode(s)?  

2) Any recommendations with respect to the cable to use for the external loopback mode?  

3) Is there a verification test-bench that can be ran in simulation and/or on the board (e.g. Packet A produces packet B on port X)? 

4) What documentation exist that describes the interaction of the SRIO and GTX?


 All responses, minute and large, are greatly appreciated.





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