09-21-2018 10:06 AM
When simulating the example design in Vivado 2017.4, with the CMAC configured in RX simplex mode, and with SIM_SPEED_UP defined (as shown here), RX alignment is not achieved until ~1.5 ms:
Here are my simulation settings:
In the log I do see:
"xvlog --incr --relax -d SIM_SPEED_UP -prj cmac_rx_exdes_tb_vlog.prj"
What am I doing wrong?
09-27-2018 08:01 AM
How long have you run the simulation? It could take ~30mins with Questa and maybe double in XSIM.
It isn’t possible to sim in loopback though since 100G AN doesn’t complete in loopback – requires connecting up 2 cores released from reset at different times or with different NONCE seed values.
09-27-2018 09:32 AM - edited 09-27-2018 09:37 AM
I don't recall exactly how long it took to get to 1.5 ms, but it was several hours. Alignment DID occur eventually. This is the example design, so two separate cores were connected together. I didn't change anything, except to set SIM_SPEED_UP.
If 1.5 ms is the expected amount of time for RX alignment, that's fine. I was just expecting it to occur more quickly based on comments in other threads.