Virtex6 GTX exmaple design seems not working with ISE 11.5

[jaekang]

MGT example design generated from GTX transciever wizard is not working after updating to ISE 11.5.

I got gtx plldetect but couldn't get gtx_resetdone. gtx reset is initiated by MMCM's "locked" so looks like MMCM ican't be locked in certain reason.

Same example was working fine with ISE 11.4 on exactly same eval board, ML605.

The only change I made is a modification of MMCM pll parameters according to AR#33849 and #34143. Virtex6 MMCM VCO should be >600MHz and MULT_F>5.

After running clock wizard, I got new value of MULT_F = 8, DIVCLK_DIVIDE=2 with clock input 125MHz.  MMCM calibration circuit needed for ISE 11.4 or previous version would be automatically inserted from 11.5.

Any advice would be appreciated.

[ywu]

This is probably not what's causing your problem, but based on your Fin=125MHz, M=8 and D=2, the Fvco is calculated to 500MHz (=Fin*M/D). Did your design actually go through 11.5 without any DRC error with these parameters?

[jaekang]

Thanks Jim.

Actually MMCM clock input is 250MHz in my example design.

The clock scheme in the design is that user clock input(125MHz) goes to GTX reference clock input first. Then GTX txpll output (TXOUTCLK:250MHz)  drives MMCM to make userclk and userclock2 for multiple GTXs as in GTX user guide. So VCO must be 1GHZ.

I used exactly same clock setup and passed through data successfully with 11.4 but MMCM seem not locked anymore with 11.5.

[kka]

Can you provide following details:

1. Line rate

2. Do you use REFCLKOUT or TXOUTCLK for MMCM input?

3. Device/speedgrade

[jaekang]

1. Line rate: 2.5Gbps

2. TXCLKOUT used for MMCM input

3. Virtex6 240T-1 is on ML605 board

MMCM generates userclock(125MHz), userclock2(250MHz) for GTX and user logic.

The GTX clock system is like figure 3-7, page 85 GTX UG366.

[kka]

I feel something wrong in the details you gave.

Either Line rate or user clk/user clk2 value is wrong.

For 2.5 Gbps,

User clk/User clk2 values is 125MHz/62.5MHz (i assume 8B/10B encoding)

If you need user clk/user clk2 of 250MHz/125Mhz, line rate should be 5.0 Gbps

Btw, how did you arrive the userclock(125MHz), userclock2(250MHz) rates?

[jaekang]

For FPGA Tx interface datapath configuration, my case is first row of Table 3-1 pag78 UG366:

TXENC8B10BUSE=1, TX_DATA_WIDTH=10bits, FPGA Interface Width=8bits, Internal Data Width=20bits

With these values, TXUSRCLK rate = Line rate / Internal Datapath Width = 2.5 Gbps / 20bit = 125 MHz ------------- Eq3-1 UG366

TXUSRCLK2 = 2 x TXUSRCLK = 250 MHz --------------------- first row in Table 3-4 UG366

I used GTX transciever wizard to generate above value. Also I used clock wizard to meet MMCM paramters requirement, VCO/MULT_F.. I used same clock system for my design with 11.4 w/ or w/o workaround and worked fine.

Thanks