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10,196 Views
Registered: ‎12-22-2014

Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Good Morning Internet,

 

I am using Vivado 2014.3 and trying to generate an Serial RapidIO Gen2 v3.2 core that includes the example/simulation design that impliments two connected cores and stimulus. When used, the core is generated, but the example files are not generated. I have searched the GUI for clues and options. In previous ISE versions, you could choose whether to generate the example code or not.

 

The documentation for the Serial RapidIO Gen2 v3.2 indicates that the example design directory should be placed in <project_dir>/<component_name>_example/<component_name>_example.srcs/sources_1/imports/example_design

 

my file structure does not include the <project_dir>/<component_name>_example directory. Could someone point me to the GUI option that I have missed or let me know if this feature is documented, but not included in the 3.2 release? Are the files located else where? The IPCore generator does create an srio_gen2_0_funcsim.vhdl. That is the closest to an example simulation file I can find.

 

This is my first forum post ever, so, yes, it is that frustrating.... Any help from would be a great holiday gift.

 

 

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
17,265 Views
Registered: ‎02-06-2013

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Hi

 

Select reset output products and then deselect the ooc option as shown below and then click ok.

 

Then you should be able to see the open IP example design high lighted.

 

srio_ooc.png

Regards,

Satish

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8 Replies
Xilinx Employee
Xilinx Employee
10,191 Views
Registered: ‎02-06-2013

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Hi

 

 

You need to right click on the xci file and you will be seeing an open example design option which will create the example

design when you select the option.

 

Check below snapshot

srio.png

Regards,

Satish

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10,185 Views
Registered: ‎12-22-2014

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Thanks for the quick reply. However, my menu does not give that as an active option. Any ideas?

 

My license info is below.

 

 

 

 

xilinx.png

 

 

 

 

xilinx2.JPG

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Xilinx Employee
Xilinx Employee
17,266 Views
Registered: ‎02-06-2013

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

Jump to solution

Hi

 

Select reset output products and then deselect the ooc option as shown below and then click ok.

 

Then you should be able to see the open IP example design high lighted.

 

srio_ooc.png

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Observer deanbruce
Observer
9,673 Views
Registered: ‎01-19-2015

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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I have a similar problem, i cant open the example design.

both reset output products and out of context settings are greyed out for srio_gen2

 

any ideas?

 

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Xilinx Employee
Xilinx Employee
9,667 Views
Registered: ‎02-06-2013

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Hi

 

Can you show us a snapshot and flow you are following where you are seeing this issue?

Regards,

Satish

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Observer deanbruce
Observer
9,658 Views
Registered: ‎01-19-2015

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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I have created a new project and instantiated the SRIO IP without any connections.

As you can see the open IP example design is greyed out.

 

I am using a zc706 dev board device locked licence. do i need to upgrade my licence file to add the srio eval before opening the example design?

 

 

screencapture.png

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Xilinx Employee
Xilinx Employee
9,655 Views
Registered: ‎02-06-2013

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Hi

 

The Example design option is not available in Block design.

 

You need to generate the core using IP catalog and add to the RTL project to see the example design option.

Regards,

Satish

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Observer deanbruce
Observer
9,642 Views
Registered: ‎01-19-2015

Re: Vivado 2014.3 SRIO Gen2 v3.2 example does not get generated

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Thanks for the info Satish.

 

I have now been able to open the example SRIO project.

The unfortunate thing (for me) is that the whole simulation as usual is Verilog (I use VHDL !)

 

My task now is to simply figure out what the hell it is actually doing.

Time to RTFM  :-)

 

Thanks again

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